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**Quote style:
To avoid thousands of quote marks and colliding with quote marks in
the text, I have used a modified quotation style. Anything in a
section titled "Info:" or "Features:" is a quote from a datasheet
unless otherwised stated in that section. In these sections anything
inside [] is an annotation and not part of the datasheet unless
otherwise stated in that section.
Under any other section, the text is my own unless indicated with "".
Also this document does not contain the entire datasheet for each
chip, usually only the first few pages are included to give an outline
of it. Some datasheets are 100s of pages other are only 1.
**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets.
Many chipsets state that they support VESA local bus. In some cases
these actually implement VLB somewhat like PCI, where it is entirly
decoupled from the CPU bus. Chipsets that do not state they work with
VLB, may be found on motherboards that contain VLB slots. VLB
is *basically* The 486 CPU pinout in a slot form. Unless these
m/boards contain some additional chips, there VLB implementation is
directly coupled to the CPU.
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C471/407 Green PC ISA-VLB 486 Single Chip <94
***Info:...
***Configurations:...
***Features:
o Fully IBM PC/AT Compatible. 80486DX2/DX/SX/SL Enhanced, P24D/P24T/
P24C, M6/M7 and Am486DXL/Am486DXL2 Single Chip Controller
o Supports L1 Cache Writeback CPU (P24T/P24D/M6/M7) systems
o Direct Mapped Cache Controller
- Write-Back or Write-Through Schemes
- Bank Interleave or Non-Interleave Cache
- 0/1 Wait State Cache Write Hit
- Flexible Cache Size : 32/64/128/256/512KB or 1MB
- 7 bits or 8 bits TAG addresses
- Flexible 2-1-1-1, 3-1-1-1, 2-2-2-2 and 3-2-2-2 Burst
Read/Write Timing
o Fast Page Burst Mode DRAM Controller
- 4 Banks up to 128MB of DRAMs
- 256K/512K/1M/2M/4M/16MXN DRAM Type
- Programmable DRAM Speed
- Double-sided SIMMs
o Two Programmable Non-Cacheable Regions (64KB-4MB area)
o CAS before RAS Transparent DRAM Refresh
o BIOS/Video ROM Cacheable
o Shadow RAM in Increments of 32KB
- Option to Disable Cache in Shadow RAM Area
o 256K Memory Relocation
o 8042 Emulation of Fast A2OGATE and CPU Reset
o Supports Port 92h
o Hardware/Software De-Turbo Switch
o Supports Two VL-Bus Master
o Supports Flash Memory
o Supports Double/Single frequency input
o CPU Operating frequency 0-100 MHz
o Supports Power Management Mode
- Supports the SMM and the SMI
- CPU Stop Clock Function
- Four Power Saving States
- Long and Short System Timers
- Supports the APM control
- Supports Break Switch control
- Power Saving also on non-SM] CPU
- More System Event Monitoring and the Power Saving Control
o AT Bus State Machine and Controller
o Synchronous/Asynchronous AT Bus Clock
o Programmable AT Bus Speed
- l/2,l/3,1/4,l/5,1/6,1/8,l/10 of Input Clock or 7.159MHz
o Programmable Wait State Generation
- 1 or 2 Wait States for l6-Bit Transfers
- 4 or 5 Wait States for 8-Bit Transfers
o Programmable I/O Recovery Time
o Programmable driving current for the DRAM and the ISA bus signals
o 32-Bit Data Buffer Between CPU and AT System
o Data Conversion and Swapping Logic for 32-/16-/8-Bit Transfers
During CPU and DMA Cycles
o Data Latches for AT Read Cycles
o Parity Generation and Detection Logic
o Port B Register and NMI Logic
o Integrated Peripheral Controllers
- 8259A x2 / 8237x2 / 8254 / 74LS612
o 387/487SX and Weitek 3167/4167 Coprocessors Interface
o 208-Pin PQFP
o 0.8nm Low Power CMOS Technology
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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