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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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**82C700         FireStar                                         c:97
***Info:...
***Configurations:...
***Features:...
**82C701         FireStar Plus                                    c:97
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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*Unresearched:...
*VIA...
*VLSI...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?
***Info:
The VL82C3216 Bus Expanding  Controller (BANC) Cache with Write Buffer
is  specifically  designed  to  provide a  high-performance,  low-cost
solution for  interfacing 386SX  PC/AT-compatible chip sets  to 386DX,
Am386DXL,  AM386DXLV,  486DX,  486SX,  or compatible  processors.  The
designs  may   be  entirely  new  systems  or   upgrades  to  existing
ones. Power management features also make this device ideal for laptop
computers  or  other battery  operated  systems.   The performance  is
achieved  through the  use of  a write  buffer structure,  an external
second level cache, prediction algorithms, and maximizing the internal
first level cache of the i486, if used.

The  high  level of  integration  is  entered  on the  VL82C3216.   It
controls all  functions between the  host processor bus and  the 386SX
local  bus.   in  addition  the  the  write  buffer  and  second-  and
first-level  cache controls,  the  VL82C3216  contains prediction  and
burst mode algorithms that take full advantage of the page mode design
of existing 386SX  system architecture.  Through the  use of pipelined
page mode accesses to system memory,  the VL82C3216 bursts data to and
from memory at rates  of up to 25 MB per  second. This provides 32-bit
memory performance at 16-bit memory costs.
 
***Versions:...
***Features:...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
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**Other:...
**Not sure if they actually exist...
*Western Digital...
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*ZyMOS...
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