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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
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*OPTi...
**82C700 FireStar c:97
***Info:...
***Configurations:...
***Features:
PCI Bus
o PCI supports sustained X-1-1-1 bursts, even to DRAM through an
innovative mechanism. PCI operation can be concurrent with
CPU/L2 cache and IDE operations.
o PCI clock generation eliminates the need for external PCI clock
buffers in many designs and allows the PCI bus to be effectively
power-managed.
o 3.3V or 5.0V PCI is supported on the FireStar PCI bus. If FireStar
is configured for 3.3V operation, 5.0V-only PCI plug-in cards and
docking stations can still be supported through a bridge device
such as OPTi's 820824 Cardbus Controller/Docking Solution, whose
prefetch and post-write buffers off-load operations from the
primary PCI bus.
DRAM Controller
o Provides BIOS with the means to automatically detect the DRAM type
in use on each bank, whether fast page mode, EDO, or synchronous
DRAM, allowing BIOS routines to efficiently program DRAM
operation.
ISA Bus
o A full ISA bus is directly provided to support the keyboard
controller, BIOS ROM, and Compact ISA peripheral devices for local
ISA support with no TTL. When reduced ISA operation is selected,
other FireStar pins become available for general purpose use.
Bus Mastering IDE
o FireStar supports two bus mastering IDE channels that function
concurrently with operations on the CPU/L2 cache interface and PCI
interface. Up to four drives are supported.
o An emulated bus mastering IDE feature allows IDE drives that are
not commonly available as bus mastering devices, such as CD-ROM
drives, to act as bus mastering drives. For example, a CD-ROM
drive can transfer video data to DRAM while the CPU is
decompressing the data and sending it to the graphics controller.
Thermal Management
o Fail-safe thermal management incorporates feedback logic that
requires a very inexpensive external sensor circuit.
o Hardware monitors temperature directly and reliably, while the
fail-safe aspect of the circuitry ensures that sensor component
failure will automatically inhibit CPU clocking to prevent
overheating.
o SMM code will be able to read (and display if desired) actual CPU
temperature.
ACPI Implementation
o Microsoft Advanced Configuration and Power Interface (ACPI) is
being implemented in the FireStar silicon. ACPI is a standard
register interface for power management function jointly developed
by Microsoft, Intel, and Toshiba.
Miscellaneous
o The standard version of the chip can run at 3.3V, up to 66MHz on
the CPU bus.
o A new Context Save Mode feature allows chip registers to be saved
and restored more efficiently than ever before, requiring less SMM
code and storage space.
o The OPTi Viper-N+ Power Management Unit is used, maintaining
backward compatibility down to the register level with previously
written support firmware.
o Serial IRQs are supported as an option for interrupts on PCI.
o Known devices in the system can be positively decoded on the PCI
bus, eliminating the delay for subtractive decode and improving
the efficiency of ISA operations.
o ISA bus cycle speed can be individually controlled to certain ISA
device groups.
o Simple logic gate functions can be assigned to unused pins to
eliminate the need for external TTL. Pin programming is far more
flexible than ever possible on any other chip.
**82C701 FireStar Plus c:97
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?
***Info:...
***Configurations:...
***Features:...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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