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**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?
***Info:...
***Configurations:...
***Features:...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C683         386/486AWB EISA [no datasheet]                      ?
***Notes:...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97
***Info:...
***Configurations:...
***Features:
PCI Bus
o   PCI supports sustained X-1-1-1 bursts, even to DRAM through an 
    innovative mechanism. PCI operation can be concurrent with 
    CPU/L2 cache and IDE operations.
o   PCI clock generation eliminates the need for external PCI clock 
    buffers in many designs and allows the PCI bus to be effectively 
    power-managed.
o   3.3V or 5.0V PCI is supported on the FireStar PCI bus. If FireStar 
    is configured for 3.3V operation, 5.0V-only PCI plug-in cards and 
    docking stations can still be supported through a bridge device 
    such as OPTi's 820824 Cardbus Controller/Docking Solution, whose 
    prefetch and post-write buffers off-load operations from the 
    primary PCI bus.
DRAM Controller
o   Provides BIOS with the means to automatically detect the DRAM type 
    in use on each bank, whether fast page mode, EDO, or synchronous 
    DRAM, allowing BIOS routines to efficiently program DRAM 
    operation.
ISA Bus
o   A full ISA bus is directly provided to support the keyboard 
    controller, BIOS ROM, and Compact ISA peripheral devices for local 
    ISA support with no TTL. When reduced ISA operation is selected, 
    other FireStar pins become available for general purpose use.
Bus Mastering IDE
o   FireStar supports two bus mastering IDE channels that function 
    concurrently with operations on the CPU/L2 cache interface and PCI 
    interface. Up to four drives are supported.
o   An emulated bus mastering IDE feature allows IDE drives that are 
    not commonly available as bus mastering devices, such as CD-ROM 
    drives, to act as bus mastering drives. For example, a CD-ROM 
    drive can transfer video data to DRAM while the CPU is 
    decompressing the data and sending it to the graphics controller.
Thermal Management
o   Fail-safe thermal management incorporates feedback logic that 
    requires a very inexpensive external sensor circuit.
o   Hardware monitors temperature directly and reliably, while the 
    fail-safe aspect of the circuitry ensures that sensor component 
    failure will automatically inhibit CPU clocking to prevent 
    overheating.
o   SMM code will be able to read (and display if desired) actual CPU 
    temperature.
ACPI Implementation
o   Microsoft Advanced Configuration and Power Interface (ACPI) is 
    being implemented in the FireStar silicon. ACPI is a standard 
    register interface for power management function jointly developed 
    by Microsoft, Intel, and Toshiba.
Miscellaneous
o   The standard version of the chip can run at 3.3V, up to 66MHz on 
    the CPU bus.
o   A new Context Save Mode feature allows chip registers to be saved 
    and restored more efficiently than ever before, requiring less SMM 
    code and storage space.
o   The OPTi Viper-N+ Power Management Unit is used, maintaining 
    backward compatibility down to the register level with previously 
    written support firmware.
o   Serial IRQs are supported as an option for interrupts on PCI.
o   Known devices in the system can be positively decoded on the PCI 
    bus, eliminating the delay for subtractive decode and improving 
    the efficiency of ISA operations.
o   ISA bus cycle speed can be individually controlled to certain ISA 
    device groups.
o   Simple logic gate functions can be assigned to unused pins to 
    eliminate the need for external TTL. Pin programming is far more 
    flexible than ever possible on any other chip.


**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
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