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**82C110   IBM PS/2 Model 30/Super XT                                ?
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
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*Contaq  . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*HMC (Hulon Microelectronics)...
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**82C281/282     Cache Sx/AT         (386SX)                 <08/22/91
***Notes:...
***Info:
The 82C281/2 is a highly integrated  AT system logic VLSI for high end
386 Sx AT systems. It integrates  the logic for local DRAM control, AT
bus  control,  cache memory  control,  and  data  bus control  and  is
designed for systems running at 16MHz, 20MHz, and 25MHz.

A high performance, compact 386 Sx/AT system can be implemented easily
with 82C281/2  and standard peripheral controllers like  the 82C206 or
the VLSI 82C100 plus Dallas Semiconductor DS1287.

2 System Operation
The following sections describe  the detailed system operations of the
82C281 /2 based Sx-AT design.

2.1 Reset
The power good (PWRGD) signal from power supply drives the system into
the initial state when it is asserted low. The 82C281/2 forces CPURST,
SYSRST, and  NPRST high as soon  as PWRGD becomes inactive.   When the
PWRGD  is high,  the chip  deactivates the  CPURST, SYSRST,  and NPRST
after 128 CLK2 cycles.

2.2 Cache Interface
The 82028112 cache control unit monitors the HIT# pin and the internal
NCA#  signals  to  determine if  it  is  a  cache  hit or  cache  miss
cycle. During the cache read  miss cycle, the cache controller asserts
TAGWE# to  update the TAG  RAM, CAWE# is  also asserted to  update the
cache data memory.

The A1 CNT  output will be forced high then low  to toggle CPU address
bit 1 to cache data memory to achieve the prefetch.

During cache write hit cycles,  the cache controller asserts the CAWE#
signal to update the cache data memory.

2.3 Local DRAM Interfaces
Local DRAM is located  on the CPU local data bus and  is buffered by a
F244 and F373 buffer.  During CPU read cycles data is routed from main
memory to CPU through F244’s Which  are controled by LMRD#. During CPU
write cycles,  data is latched by  F373 latches with the  PDLTH signal
from the  82C281/2 while DWE#  controls the transceivers'  enable. The
main memory subsystem  asserts the LMRD# while CPU,  DMA, and external
master card reads  the local DRAM. DWE# is asserted  during local DRAM
memory write.

For local memory read cycles, the memory controller reads two bytes at
a time. The  read data passes into 82C281/2  where the parity checking
function is executed.

For the local memory write cycles, the data bus control unit generates
the parity bits to be stored into the local DRAM.

2.4 System BIOS ROM
If the system BIOS ROM is  not shadowed, the ROM cycles are treated as
AT cycles.  The system designer can  put the ROM  on the XD bus  as an
8-bit slave or SD bus as a 16-Bit slave.

For  a 16-bit  slave,  ROMCS# is  connected  to M16#  through an  open
collector  driver  such as  a  7407,  the  82C281/2 monitors  M16#  to
determine the width of the ROM data path.

2.5 I/O Ports located on the XD bus
For l/O ports located on the XD bus, the XDIR# is activated. I/O ports
0F0H - 0FFH are reserved for the coprocessor.

2.6 Refresh Cycles
The AT  bus control unit arbitrates  the hold request  from 82C206 and
the refresh request from 82C281/2  internal, then decides which is the
next  owner of  the bus  once the  CPU relinquishes  it.   The refresh
request generated  internally by 82C281/2  can be programmed  as every
15.9  micro-seconds  or  every  95.5 micro-seconds  for  slow  refresh
DRAM. lf  the bus is  granted for refresh  cycles, the AT  bus control
unit asserts RFSH# and MEMRD#  commands and also generates the refresh
address.

2.7 DMA Cycles
The hold  request from the 82C206 initiates  DMA/Master transfers. The
82C281/2   performs   the   arbitration   between  HRQ   and   refresh
request. After the CPU acknowledges by asserting HLDA, and DMA request
wins  the  arbitration,  the   82C281/2  sends  HLDA1  to  the  82C206
acknowledging  the  request.  The   820206  then  asserts  DMA16#  and
activates ADS16# to  start 16-bit DMA transfers, or  asserts DMA8# and
activates ADS8# to start 8-bit DMA transfers.

***Configurations:...
***Features:...
**82C283         386SX System Controller                          c:91...
**82C291         SXWB PC/AT Chipset  (386SX)                      c:91...
**82C295         SLCWB PC/AT Chipset (386SX)                         ?...
**82C381/382     HiD/386             (386DX)                      c:89...
**82C391/392     386WB PC/AT Chipset (386DX)                    <Dec90...
**82C461/462     Notebook PC/AT chipset [no datasheet]               ?...
**82c463         SCNB Single Ship Notebook                        c:92...
**82c465MV/A/B   Single-Chip Mixed Voltage Notebook Solution    <Oct97...
**82C481?/482?   HiP/486 & HiB/486 [no datasheet]                Oct89...
**82C491/392     486WB PC/AT Chipset                         <04/21/91...
**82C493/392     486SXWB                                     <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet]                   ?...
**82C495SLC      DXSLC 386/486 Low Cost Write Back                c:92...
**82C495XLC      PC/AT Chip Set                                   c:93...
**82c496A/B      DXBB PC/AT Chipset                             <Mar92...
**82C496/7       DXBB PC/AT Chipset (Cached)                 <01/16/92...
**82C498         DXWB PC/AT chipset [no datasheet]                   ?...
**82C499         DXSC DX System Controller                        c:93...
**82C546/547     Python PTM3V                                     c:94...
**82C556/7/8     Viper [no datasheet]                                ?...
**82C556/7/8N    Viper-N  Viper Notebook Chipset             <05/25/95...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?
***Info:...
***Configurations:...
***Features:...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
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*TI (Texas Instruments)...
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*VIA...
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