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**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor to form a CPU Cache chip set designed for high
performance servers and function-rich desktops. The high speed
interconnect between the CPU and cache components has been optimized
to provide zero-wait state operation. This CPU Cache chip set is
fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82496 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit wide memory bus widths, 16, 32, and 64 byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82491, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82c463 SCNB Single Ship Notebook c:92
***Info:...
***Configurations:...
***Features:
General Features:
o Supports 3.3V and 5V Intel, AMD & Cyrix SMI 486 CPUs and the "NEW"
Intel Low Power 486 CPUs
o True single chip notebook implementation (internal '206) based on
the proven 82C461/462 core.
o Single 208-pin PQFP package implemented in 0.8u CMOS technology
o 100% IBM AT compatible solution
o Supports operation up to 33Mhz at 5V and 25Mhz at 3.3V
o Fully supports local bus implementations, including VESA VL-bus
o Supports Sequencer microcode, System BIOS and Video BIOS combined
in a single 8-bit ROM
o Option for Write protected, cacheable video and system BIOS
o Emulation of fast CPU reset and gate A20, as well as port 92h
support
o Standard system requires only six TTL plus a Real Time Clock (RTC)
o Test mode support for in-circuit testing
o Two programmable chip selects and exter software utility timer
DRAM Controller Features:
o Page-mode DRAM controller supports 2-1-1-1, 3-1-1-1, 3-2-2-2 and
4-3-3-3 burst read memory cycles.
o DRAM controller supports zero wait state DRAM write cycles
o Supports for banks of 256K, 512K, 1M and 4M DRAMs for
configurations up to 64MB
o Support for two programmable non-cacheable regions
o Fully programmable shadow RAM in C0000h-FFFFFh
o Slow refresh, CAS before RAS refresh and self-refresh support.
Power Management Features:
o Supports SMI features for Intel, AMD & Cyrix SMI CPUs and the
"NEW" Intel Low Power 486 CPUs
o Sequencer power management, with enhanced features over the
82C461/462 Sequencer
o Full Microsoft APM support, with CPU stop-clock support
o Support for CPU clock stretch function
o Supports system-level zero-volt suspend
o Flexible power saving modes with support for individual peripheral
time-outs
o Operating system & application independent power management (no
device drivers needed)
o 16 PMI event sources to generate SMI or to activate Sequencer
o Supports I/O trap for peripheral device power control
o Eight peripheral power control pins plus four user definable
I/O pins
o RTC alarm or modem ring auto wake-up
o Suspend current leakage control
o Static AT-bus clock when AT-bus is idle.
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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