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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.

***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**IBM AT: MC146818 Real Time Clock                                 <84
***Info:...
***Versions:...
***Features:
o   Low-Power, High-Speed, High-Density CMOS
o   Internal Time Base and Oscillator
o   Counts Seconds, Minutes, and Hours of the Day
o   Counts Days of the Week, Date, Month, and Year
o   3 V to 6 V Operation
o   Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
o   Time Base Oscillator for Parallel Resonant Crystals
o   40 to 200 uW Typical Operating Power at Low Frequency Time Base
o   4.0 to 20 mW Typical Operating Power at High Frequency Time Base
o   Binary or BCD Representation of Time, Calendar, and Alarm
o   12- or 24-Hour Clock with AM and PM in 12-Hour Mode
o   Daylight Savings Time Option
o   Automatic End of Month Recognition
o   Automatic Leap Year Compensation
o   Microprocessor Bus Compatible [this means absolutely nothing]
o   MOTEL Circuit for Bus Univerality
o   Multiplexed Bus for Pin Efficiency
o   Interfaced with Software as 64 RAM Locations
o   14 Bytes of Clock and Control Registers
o   50 Bytes of General Purpose RAM
o   Status Bit Indicates Data Integrity
o   Bus Compatible Interrupt Signals (IRQ)
o   Three Interrupts are Separately Software Maskable and Testable
      Time-of-Day Alarm, Once-per-Second to Once-per-Day
      Periodic Rates from 30.5 us to 500 ms
      End-of-Clock Update Cycle
o   Programmable Square-Wave Output Signal
o   Clock Output May Be Used as Microprocessor Clock Input
      At Time Base Frequency /1 or /4
o   24-Pin Dual-In-Line Package



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