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**82385SX     32-bit Cache Controller for 80386SX             01/25/89
***Notes:...
***Info:...
***Versions:...
***Features:...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*Headland/G2...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
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**Support Chips:
**HT44          Secondary Cache                                c:Jun92
***Info:...
***Versions:...
***Features:
General Features
o   Support for 4868X/DX/DX2 CPUs
o   System implementation with Headland’s HTK340 chip set and future 
    486 chip sets
o   16, 20, 25 and 33 MHz CPU speeds

Memory Configurations
o   32KB, 64KB, 128KB, 256KB, 512KB & 1MB cache sizes
o   25ns SRAMs required at 33 MHz
o   Asynchronous and synchronous SRAMs are supported
o   Programmable write-protected and non-cacheable regions are 
    supported through the chip set

Architecture
o   Look-Aside
o   Write through
o   Direct mapped
o   Integrated tag comparator
o   Zero wait state cache hits
o   Simultaneous 486 and secondary cache update on read miss
o   486 line burst cycle support
Package & Die
o   84-pin PLCC
o   LSI Logic’s 0.7 micron HCMOS process

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