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*_IBM...
*ACC Micro...
*ALD...
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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**Video:
F64300 Wingine DGX 2MB, (appears to be a VLB version adapted from the proprietary 64200)
F64310 Wingine DGX 2MB (appears to be a PCI version adapted from the proprietary 64200)
OC65540 VGA BIOS c:95
OC65545 VGA BIOS same as 540 but has hardware overlay feature.
94C2001 PUMA (Programmable Universal Micro Accelerator) 50MHz Video accelerator
82C840 8514/A clone
82C9001A Video controller
82C404 Programmable clock synthesizer
82C402 VGA clock Synthesizer
82C411 Flat panel color pallet/DAC
82C425 82C425 CGA, CRT+LCD support, greyscale on LCD, supports two softfonts (up to 8x16 pixels) allowing 512 characters on screen, no snow
82C426 82C426 CGA, CRT, color LCD+AT&T400 support, max 32KB RAM
82C450 82C450 1MB VRAM, max 800x600 256color
82C451 82C451 VGA 256KB DRAM, max 800x600 16color c:90
82C452 82C452 1MB DRAM, max 640x480 256color, 1024x768 16color
82C453 82C453 1MB DRAM, max 800x600 256color
82C455 82C455 256KB DRAM Flat Panel version
82C456, 456A 82C456 256KB DRAM Flat Panel/CRT
82C457 82C457 Full color
82C45x series are VGA
'The 655xx series chips are SVGA video controller chips for flat panel
displays and CRTs. They also provide some level of CGA, MDA, EGA, and
Hercules compatibility, and various accelerator features. They are
designed with various features for reducing power consumption and
optimizing display quality.
source:http://www.igl.ku.dk/~fsp/varia/ct5xx.html
see the above source for more details.
82C481 True-Color Graphics Accelerator Wingine?
F65510 65510 LCD / CRT
F65520 65520 1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color
F65525 65525 LCD / CRT
F65530 65530 1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color, VLB
F65535 65535 LCD / CRT
F65540 65540 same as 65545 but without BitBLT and hw cursor
F65545 65545 mobile, 512-1024KB DRAM, ISA / PCI / VLB
65546 65546
F65548 65548
F65550 65550 HighQV32, mobile, 1-2MB DRAM, PCI / VLB
B65554 65554 HighQV64, mobile, 1-4MB DRAM, BGA
F65555 65555 HighQVPro, mobile, 1-4MB EDO, BGA
F68554 68554 HiQVision
F68555 68555
F69000 69000
M69000 69000 HighQVideo, mobile, 83MHz RAM, 2MB SDRAM on die, PCI / AGPx1, 135MHz RAMDAC, BGA, MiniBGA
F69030 69030 HighQVideo, mobile, 100MHz RAM, 4MB SDRAM on die, PCI / AGPx1, 170MHz RAMDAC, BGA, MiniBGA
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT18 80386SX Single Chip c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92
***Notes:...
***Info:
The HTK340 chip set is a two chip, high performance, cost-effective
solution for the 80486SX DX, and DX2 processing environments. In its
minimum configuration, this highly integrated chip set requires only
four external TTL devices to implement a fully compatible IBM PC/AT
system at speeds up to 33MHZ.
The HTK340 is based upon Headland's HTK320 Bus Architecture and
consists of the HT321-ISA Bus Controller and the HT342-Memory Control
Unit (MCU). Both chips are packaged in 184 pin plastic quad flat
packs.
The HTK340 is unique in that it provides performance approximating
that of large secondary cache systems, including the highest
performance write back cache architectures, without any external
cache. Secondary cache solutions should be considered in applications
that make use of multi-tasking and large model operating systems. The
Headland HT44 secondary cache was designed to meet the cost and
performance objectives for these applications. The key to this level
of performance is the 4-level deep write buffer, which includes byte
gathering for up to 32-bit DRAM writes.
Due to the effectiveness of the primary cache internal to the 80486
most of the bus activity in a PC/AT compatible environment consists of
writes. Indeed, this write activity consists almost exclusively of
writes of either bytes or Words (16 bit entities). In addition, much
of this write activity is into sequential memory locations. The byte
gathering feature of the buffer has the effect of reducing the number
of memory accesses required. Since the 80486 can always write into the
buffer with zero wait states (assuming the buffer is not full), and
the buffer can empty faster than it can be filled for most write
activity, the net effect is that the writes from the CPU never cause a
wait state.
The HTK340 can support Peripheral Devices such as VGA or SCSI on the
local processor bus, or any other devices that are designed to work
within the 80486 bus protocol and timing. By eliminating the ISA
backplane bottleneck, system designers can greatly improve the
performance of functions such as graphics generation and disk access.
The HTK340 supports up to 4 banks of DRAM, configurable as 1-4
banks. This flexible memory architecture allows for any memory type,
from 256K to 16M devices, in any bank. Maximum system performance is
achieved from the DRAM banks through various means, including
interleaving of memory banks and/or paging, and CAS before RAS
refresh. The memory can also be tuned to maximum potential through the
use of extensive DRAM timing control registers. These controls
include: precharge time, access time on reads, active time on writes,
as well as CAS and RAS delays. In addition, further system perfor-
mance is gained by separate timing parameters on the read and write
cycles which allow system designers to take maximum advantage of the
pipelined structure of the chip set.
The HTK340 also supports extensive mapping registers, which allow
system designers to take maximum advantage of system memory. The chip
set supports Shadow/Remap in 16K blocks between the 640K and 1M
boundaries, and eliminates the requirement for external decoding logic
by supporting 26 programmable non-cache regions. Devices which meet
HTK340 local bus requirements may be implemented without external
TTL. The mapping structure of the HTK340 provides for a single 8-bit
EPROM to be used for both the System and Video BIOS, further reducing
system chip count and cost.
***Configurations:...
***Features:...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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