[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
**HT11          Single 286 AT Chip [no datasheet]               <Aug90
***Notes:...
**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Support for 486SX/DX/DX2 CPU
o   2 - 184 pin PQFP devices
o   Local bus interface
o   16, 20, 25 and 33MHz CPU speeds
o   Fully static operation
o   Weitek 4167 supported
o   System and Video BIOS on single ROM
o   Uses 0.7 Micron HCMOS process
ISA Controller
o   AT Compatible
o   Synchronized 8MHz ISA bus
o   Posted backplane memory writes
o   10 or 16 bit l/O mapping
o   Integrated 82375, 82593 and 8254 functionality
o   Fast gate A20/Fast reset
Write Buffer
o   4 deep on-chip buffer
o   Byte gathering
o   Out of order operation
o   Full or partial write buffer hits
DRAM Controller
o   Line burst capability from DRAM to 80486
o   256K/1M/4M/16M DRAMs
o   Mixed memory types
o   EMS 4.0
o   Hidden refresh operation
o   256MB Maximum system memory
o   Staggered refresh
o   Shadowing in 16KB increments between 640KB and 1MB
o   Remapping
o   Fast paging
o   2 or 4 way interleaving

**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
**J - R
***Micro Integration...
***Micron...
***Oak...
***Other:...
**S...
**T - Z...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

(c) Copyright mR_Slugs Warehouse - All rights Reserved