[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**82C601/A Single Chip Peripheral Controller                 <08/30/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT35          Single-Chip Peripheral Controller [partial info]     ?
***Notes:...
**HTK320        386DX Chip Set                                 c:Sep91
***Info:...
***Configurations:...
***Features:
o   2-chip 80386DX PC/AT compatible solution
o   Supports CPU speeds of up to 40MHz
o   3167 Weitek and 80387 co-processor supported
o   Peripherals supported on local CPU bus
o   Port 92 functions
o   Posted backplane memory cycles
Cache
o   Direct mapped or 2-way set associative cache sizes of 32K, 
    64K and 128K
o   Internal tag RAMs
o   Zero wait-state write hits
o   Line burst capability from DRAM to cache
WriteBuffer
o   4 deep, 32-bit wide write buffers
o   Byte gathering
o   Full or partial write buffer hit Support
o   Out of order operation
Memory
o   4-bank DRAM Support
o   256K, 1M, 4M, 16M support (up to 256Mb)
o   Mix and match memory types
o   2/4-way or disabled interleaving and fast paging
o   CAS before RAS, or RAS Only Refresh
o   EMS 4.0 support
o   Single BIOS-ROM support 
o   System and Video BIOS in Single ROM

**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...