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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**GC101/102 12/16MHz PC/AT Compatible Chip Set c:Feb88
***Info:...
***Configurations:...
***Features:...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0 c:Jul89...
**GCK113 80386 AT Compatible Chip Set c:oct89...
**GCK181 Universal PS/2 Chip Set c:Mar89
***Info:
The GCK181 product family provides a universal engineering platform
for PS/2 compatible systems using the Intel 80286, 80386, and 80386SX
microprocessors. This chip set introduces the most highly integrated
solution for manufacturing high performance PS/2 compatible computer
systems.
The GC181 CPU/Bus Controller initiates and controls all bus cycles. It
controls the interface to the Micro Channel, address and data buffers,
CPU, DMA and Memory Controllers. Full Micro Channel support is
provided including Matched Memory Cycles and all timing requirements.
This device also integrates reset control and clock generation
logic. It is packaged in a 68 pin PLCC.
The GC182 Memory Controller interfaces the CPU and Micro Channel to
System DRAM. Four DRAM chip sizes are supported: lMxl, 1Mx4, 256kx1,
256Kx4. These can be configured to 8 MBytes of interleaved/paged
memory. Four memory modes are selectable to meet IBM Model 50/60/70/80
memory requirements. Zero wait state page mode is achievable at 20
MHz with 80ns DRAMs. Package type is 120 pin PQFP (plastic quad flat
pack).
The GC183 DMA Controller provides 8 DMA channels, supporting 24
address bits and 8 or 16 bit data transfers. This device provides the
Micro Channel with 15 levels of bus arbitration and support for
multiple bus masters. It also contains DRAM refresh logic and NPU
support logic. Package type is 160 pin PQFP.
The GC184 Address/Data Buffer integrates approximately 44 TTL packages
otherwise required in at P8/2 system. It is packaged in a 160 pin
PQFP.
The GC186 Peripheral Controller interfaces peripherals with the Micro
Channel. It supports 15 interrupt channels, the refresh rate counter,
and three programmable timers. It also contains PS/2 POS Registers, a
PS/2 and AT compatible parallel port, address decodes for serial
ports, floppy disk, keyboard, real time clock and CMOS RAM. Package
type is 160 pin PQFP
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88
***Info:...
***Versions:...
***Features:...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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