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**Cant find a chip?
Early chip sets have a title and a part no. to refer to the chip set
as a whole. As time went on the chip set became one chip, so later
chip sets are usually referred to by the part no. on the actual chip.
These are usually called "Single Chip" by the manufacture, although
they nearly always follow the 2-chip North/South-bridge paradigm. So
these are referred to by for example, "M1521/M1523" or "M1521/M23" for
short. If there is a part number for the chip set as a whole that has
precedence. Try the search function for a chip part no. and hopefully
it will turn up the chip set it was part of.
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
**GCK113 80386 AT Compatible Chip Set c:oct89
***Info:...
***Configurations:...
***Features:
o Highly-integrated 25 MHz, AT-compatible (80386) three chip set.
o Each device includes an integral, register-level configuration
system to manage system performance.
o Software programmable wait-state generator and memory manager
that supports page mode and interleaved memory access.
o Supports 'shadow RAM' for system and video BIOS ROM.
o Supports 24 Mbytes of DRAM and either 256K or 1 Mb devices.
o Supports 128K or 64K EPROM space.
o Includes software configured decode logic for serial and
parallel I/O.
o Supports 80387 or 80287 numeric coprocessor.
o Supports connection to an EEPROM for non-volatile storage of
configuration setup data.
o Eliminates DIP switches and jumpers.
o Low board space requirements - laptop design is feasible.
o Designed in 0.9 micron HCMOS.
**GCK181 Universal PS/2 Chip Set c:Mar89
***Info:...
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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