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**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?
***Info:...
***Configurations:...
***Features:...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
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*AMD . . . . . . . [no datasheets, some info]...
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*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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**WD7615     Desktop Buffer Manager                          <04/15/92
***Info:...
***Versions:...
***Features:
o   Allows the WD7XC10 based designs to work with a generic "Super l/O" 
    device or with the WD76C20 and WD76C30
o   Replaces majority of external "glue" logic, up to 13 devices:
    - AT bus address buffers with 24 mA drive
    - AT bus interrupt multiplexing, and interrupt pull ups.
    - AT bus DRQ multiplexing and internal pull downs.
    - Keyboard/mouse interrupt latching and clearing functions
    - A20 Gate logic
    - Controlling the IDE data bit 7 at address 3F7H.
o   Allows implementation of a desktop system with only three external 
    devices
o   Direct connect to AT address bus SA1 through SA19 and LA17 through 
    LA23 with 24 mA drive
o   DAC multiplexing and RESET generation
o   DRAM WE signal from WD76C10 inversion and buffering
o   SMEMR and SMEMW generation with 24mA direct drive
o   Divide by 2 or divide by 4 clock output
o   136-pin MQFP package



**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...