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**Why this document is not GPL or a wiki
The document is copyright,  it is NOT GPL'ed text. While  the GPL is a
fantastic  idea, I  have chosen  not to  make this  freely copied  and
modified. The reasons are as follows:

1. GPL text tends to be  copied...EVERYWHERE. For example, if you look
   up a subject  on wikipedia, then try to get  more information, or a
   different perspective on  say about.com.  There you  find the EXACT
   SAME  TEXT.  This  is what  mirrors  are for.   It's an  unintended
   consequence,  but  it  can  lead  to  misinformation  being  spread
   everywhere. A bigger problem.

2. There seems to be fewer  and fewer informative websites. It used to
   be that  if you  searched for  something you  would find  a website
   about a particular  subject. Now you tend to  find the encyclopedia
   and often nothing else (well quickly).

In addition the majority of this text is quotes.

The wiki  concept is a good  idea, but they have  problems. Because no
one "owns" the  work they seem to  go to two extremes.   Either no one
maintains them, or there are edit wars. Also anyone can edit them.

**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?
***Info:
Overview

The OPTi  Viper-MAX Chipset provides a highly  integrated solution for
fully compatible, high performance  PC/AT platforms based on the Intel
3.3V  Pentium  Processor, Cyrix  6x86  Processor,  and  AMD K86  Proc-
essor. As the latest member of the Desktop Viper Chipset Family, it is
designed  from its  inception to  be the  highest  performance Pentium
chipset ever.   its feature set can  be scaled to  address entry level
UMA-based system  to high-end non-UMA work stations  and servers.  The
deep  buffers in  the Viper-MAX  minimize system  level  latencies and
maximize through-puts to both DRAM and PCI subsystems.

The chipset  provides 64-bit core  logic, with Unified  Memory Archit-
ecture  (UMA), and  integrated PCI  support, plus  sophisticated power
management  features.  This  highly integrated  approach  supplies the
foundation  for a  cost effective  platform without  compromising per-
formance. Its  feature set  furnishes an array  of control  and status
monitoring options  that are accessed  through a simple  and straight-
forward interface.  All major BIOS vendors  provide extensive software
hooks  that allow  system  designers to  integrate  their own  special
features with minimal effort.

82C566 Data Buffer Controller
The 82C566 performs  the task of buffering the CPU  to the DRAM memory
data path.

o   CPU to memory data buffer
o   CPU to PCI local bus buffer
o   Memory to PCI local bus buffer
o   208-pin PQFP

82C567 System Controller
The 82C567 provides the control  functions for the host CPU interface,
the  64-bit Level-2  (L2)  cache, the  64-bit  DRAM bus,  and the  PCI
interface. The 82C567 controls the  data flow between the CPU bus, the
DRAM bus, the local buses, and the 8/16-bit ISA bus. It interprets and
translates cycles from the CPU, PCI bus master, ISA master, and DMA to
the host  memory, PCI bus slave,  or ISA bus devices.  The 82C567 also
serves  as the UMA  (Unified Memory  Architecture) and  USB (Universal
Serial Bus) protocol interface.

o   3.3V CPU interface
o   DRAM controller
o   L1/L2 cache controller
o   UMA arbiter
o   USB interface
o   PCI interface
o   Arbitration logic
o   Data bus buffer control (memory data bus to and from host data 
    bus)
o   208-pin PQFP

82C568 Integrated Peripherals Controller
The 820568 contains the ISA bus controller and includes an 82C206, RTC
interface, DMA controller, serial interrupt controller and distributed
DMA. It also has a sophisticated system power management unit.

o   ISA bus controller
o   Master mode IDE
o   Type F DMA support
o   Integrated 82C206 IPC
o   System power management functions
o   PCI local bus interface
o   PCI to ISA expansion bridge
o   Serial interrupt controller
o   Distributed DMA
o   Keyboard emulation of A20M# and CPU warm reset
o   Port B and Port 092h Register
o   208-pin POFP

***Configurations:...
***Features:...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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