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**82385SX 32-bit Cache Controller for 80386SX 01/25/89
***Notes:...
***Info:...
***Versions:...
***Features:...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
**800 series...
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*UMC...
**UM82C380 386 HEAT PC/AT Chip Set <91
***Info:
The UMC's HEAT (High End AT) Chip Set UM82C380 is a highly integrated,
flexible solution for high performance 80386 PC/AT compatible systems.
Fabricated using advanced 1 .2u. CMOS VLSI technology, it provides
high reliability, low power, low chip count features for system
implementation. A commercial 25MHz/0 wait state. 12MByte main memory
system with cache memory control and math-coprocessor features can be
easily built in a standard baby AT size mother board (12" x 8.6") with
all necessary components included.
The UM82C380 series consists of five chips, the UM82C381 System
Controller, UM82C382 Address Buffer, UM82C383 Data Buffer, UM82C384
Memory Controller and UM82C388/389 Cache Interface. Combined with
UMC's UM82C206 Integrated Peripheral Controller, the chip set forms a
highly integrated solution for 25MHz 80386 PC/AT systems with
Page/Cache Mode options.
The UM82C380 series supports a local 32-bit CPU/MP bus, a 32-bit
memory data bus, a 16-bit AT channel bus, an 8 bit I/O channel
peripheral data bus and 8MHz system clock to provide the best
compatibility with industry standards.
The UM82C381 is a System Controller. It provides all four bus control
signals, synchronized reset for CPU and peripherals, refresh control,
math-coprocessor (80287/80387) interface, address decoding logic,
CLK2, BCLK and timer clock generation.
The UM82C382 is an Address Buffer. It provides address interface to
processor address, system address, DMA address XA and latched XD
bus. A 10-bit refresh counter is included for both 256K and 1M DRAM
refresh.
The UM82C383 is a Data Buffer. It provides bus interface for CPU local
data bus, system data bus and peripheral data bus. Word-swap logic is
also built in to facilitate the 80386 read or write 32-bit data
through PC/AT 16-bit data bus.
The UM82C384 is a Memory Controller. It provides control for 32-bit
memory data bus, memory paging control for 256K and 1M DRAM, RAS and
CAS control for system memory.
The UM82C388 is a Cache interface. It provides a simple DRAM
controller to interface INTEL 82385 Cache controller with the system
memory.
The UM82C389 is another Cache Interface. It also provides a simple
DRAM Controller to interface UM82152 Cache Controller with the System
Memory, it has been highly integrated for easy application.
Basically, three different 80386 PC/AT system configurations can be
implemented using UM82C380 series HEAT chip set. These are Page Mode,
UM82152 Cache Control Mode, and INTEL 82385 Cache Control Mode. All
three mode implementations will require the four common core logic
devices of HEAT chip set; UM82C381 , UM82C382, UM82C383 and
UM82C206. The UM82C384 will be needed for Page Mode , while UM82C389
and UM82C388 are needed for UM82152 and 82385 Cache Control Modes. The
block diagrams and the required IC list for each system configuration
is illustrated in Figures 1 ,2, and 3 [see datasheet].
A software driver is required to initiate the UM82152 when the system
is working in UM82152 Cache Control Mode. A PAL equation is needed to
implement the HEAT chip set working in INTEL 82385 Cache Control
Mode. Either or both of these tools can be requested from UMC's
worldwide sales offices.
***Configurations:...
***Features:...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
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*Winbond...
*ZyMOS...
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