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**82385 32-bit Cache Controller for 80386 09/29/87
***Notes:...
***Info:
The 82385 Cache Controller is a high performance 32-bit peripheral for
Intel's 80386 Microprocessor. It stores a copy of frequently accessed
code and data from main memory in a zero wait state local cache
memory. The 82385 enables the 80386 to run at its full potential by
reducing the average number of CPU wait states to nearly zero. The
dual bus architecture of the 82385 allows other masters to access
system resources while the 80386 operates locally out of its cache.
In this situation, the 82385's "bus watching" mechanism preserves
cache coherency by monitoring the system bus address lines at no cost
to system or local throughput.
The 82385 is completely software transparent, protecting the integrity
of system software. High performance and board savings are achieved
because the 82385 integrates a cache directory and all cache
management logic on one chip.
1.0 82385 FUNCTIONAL OVERVIEW
Th~ 82385 Cache Controller is a high performance 32-bit peripheral for
Intel's 80386 microprocessor. This chapter provides an overview of
the 82385, and of the basic architecture and operation of an 80386/
82385 system.
1.1 82385 OVERVIEW
The main function of a cache memory system is to provide fast local
storage for frequently accessed code and data. The cache system
intercepts 80386 memory references to see if the required data resides
in the cache. If the data resides in the cache (a hit), it is returned
to the 80386 without incurring wait states. If the data is not cached
(a miss), the reference is forwarded to the system and the data
retrieved from main memory. An efficient cache will yield a high "hit
rate" (the ratio of cache hits to total 80386 accesses), such that the
majority of accesses are serviced with zero wait states. The net
effect is that the wait states incurred in a relatively infrequent
miss are averaged over a large number of accesses, resulting in an
average of nearly zero wait states per access. Since cache hits are
serviced locally, a processor operating out of its local cache has a
much lower "bus utilization" which reduces system bus bandwidth
requirements, making more bandwidth available to other bus masters.
The 82385 Cache Controller integrates a cache directory and all cache
management logic required to support an external 32 Kbyte cache. The
cache directory structure is such that the entire physical address
range of the 80386 (4 Gigabytes) is mapped into the cache. Provision
is made to allow areas of memory to be set aside a non-cacheable. The
user has two cache organization options: direct mapped and 2-way set
associative. Both provide the high hit rates necessary to make a
large, relatively slow main memory array look like a fast, zero wait
state memory to the 80386.
A good hit rate is an essential ingredient of a successful cache
implementation. Hit rate is the measure ,of how efficient a cache is
in maintaining a copy of the most frequently requested code and data.
However, efficiency is not the only factor for performance
consideration. Just as essential are sound cache management
policies. These policies refer to the handling of 80386 writes,
preservation of cache coherency, and ease of system design. The
82385's "posted write" capability allows 80386 memory writes,
including non-cacheable, to run with zero wait states, and the 82385's
"bus watching" mechanism preserves cache coherency with no impact on
system performance. Physically, the 82385 ties directly to the 80386
with virtually no external logic.
***Versions:...
***Features:...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**Later Chipsets:
Info sourced from the very useful plasma-online.de:
http://www.plasma-online.de/index.html?content=http%3A//www.plasma-online.de/english/identify/picture/pcchips.html
Chipset name | OEM of | used on mainboard
---------------+---------------------------+-----------------------------------------
HX Pro | ALi M1521/M1523 |
SX Pro | SiS 530/5595 | M598
AGP Pro PC-100 | VIA VT82C598AT/VT82C596B | M577
TX AGP Pro | SiS 5591/5595/6326 |
TX Two | ALi M1531/M1543 |
TX Pro | ALi M1531/M1543 | M560, M575
TX Pro II | SiS 5597/5598 | M571
TX Pro III | VIA VT82C580VPX/VT82C586B | M573
TX Pro IV | SiS 5591/5592 | M570
Top Gun | ALi Aladdin IV+ | M565
VIA GRA | VIA VT8501/VT82C596B | M858LMR
VX Pro | VIA VT82C580VP/VT82C586B |
VX Pro + | VIA VT82C580VPX/VT82C586B |
VX Pro II | UTron / HiNT UT801X |
VX two | VIA VT82C580VP/VT82C586B | Amptron PM-8600A
VX two | VIA VT82C580VPX/VT82C586B | Amptron PM-8600B
BXToo | VIA Apollo Pro | M760V, M761V
BXToo | VIA VT82C693/VT82C686A | M767V
BXPro | SiS 600/5595 | M747
BXCel | ALi M1621/M1543 | M726, M729
BXpert | VIA VT82C691/VT82C596 |
BXTel | VIA Apollo Pro | M730
Xcel 2000 | SiS 620/5595 | M741LMRT
Super TX | SiS 5597/5598 | ASUS SP97-V, SP98-N, Jetway J-TX98R2
Super TX | ALi M1531/M1543 |
Super TX | ALi M1541/M1543 | Biostar M5ALA, M5ALC, Pionex MBD-P5ABx
Super TX3 | SiS 5571 |
Super TX4 AGP | |
GFXcel | SiS 630 |
GFXpro | ALi M1631/M1535D |
T-Bird | SiS730S | M810
---------------+---------------------------+----------------------------------------
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