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**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95
***Notes:...
***Configurations:...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
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**M1535/D South Bridge ?...
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*Intel...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97
***Notes:...
***Info:
The Intel 430TX PCIset (430TX) consists of the 82439TX System
Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator (PIIX4). The
430TX supports both mobile and desktop architectures. The 430TX forms
a Host-to-PCI bridge and provides the second level cache control and a
full function 64-bit data path to main memory. The MTXC integrates the
cache and main memory DRAM control functions and provides bus control
to transfers between the CPU, cache, main memory, and the PCI Bus. The
second level (L2) cache controller supports a writeback cache policy
for cache sizes oi 256 Kbytes and 512 Kbytes. Cacheless designs are
also supported. The cache memory can be implemented with pipelined
burst SRAMs or DRAM cache SRAMs. An external Tag RAM is used for the
address tag and an internal Tag RAM for the cache line status
bits. For the MTXC DRAM controller, six rows are supported for up to
256 Mbytes of main memory. The MTXC is highly Integrated by including
the Data Path into the same BGA chip. Using the snoop ahead feature.
the MTXC allows PCI masters to achieve full PCI bandwidth. For
increased system performance. the MTXC integrates posted write and
read prefetch buffers. The 430TX integrates many Power Management
features that enable the system to save power when the system
resources become idle.
1.0. ARCHITECTURE OVERVIEW
The MTXC host bridge provides a completely integrated solution for the
system controller and datapath components in a Pentium processor
system. The MTXC Supports all Pentium family processors since P54C, it
has 64-bit Host and DRAM Bus Interface, 32-bit PCI Bus Interface,
Second level Cache Interface, and it integrates the PCI arbiter.
The MTXC interfaces with the Pentium processor host bus, a dedicated
memory data bus, and the PCI bus (see Figure 1) [see datasheet].
The MTXC bus interfaces are designed to interface with 2.5V, 3.3V and
5V busses. The MTXC implements 2.5V and 3.3V drivers and 5V tolerant
receivers. The MTXC connects directly to the Pentium processor 3.3V or
2.5V host bus, directly to 5V or 3.3V DRAMs, and directly to the 5V or
3.3V PCI bus. The 430TX also interfaces directly to the 3.3V or 5.0V
TAGRAM and 3.3V Cache.
The MTXC works with the PCI IDE/ISA Accelerator 4 (PIIX4). The PIIX4
provides the PCI-to-ISA/EIO bridge functions along with other features
such as a fast IDE interface (PIO mode 4 and Ultra DMA/33),
Plug-n-Play port, APIC interface, PCI 2.1 Compliance. SMBUS interface,
and Universal Serial Bus Host Controller functions.
DRAM Interface
The DRAM interface is a 64-bit data path that supports Standard (or
Fast) Page Mode (FPM), Extended Data Out (EDO) and Synchronous DRAM
(SDRAM) memory. The DRAM controller inside the MTXC is capable of
generating 3-1-1-1 for posted writes for any type of DRAM that is
used. While read performance is 6-1-1-1 for SDRAM, 5-2-2-2 for EDO,
and 6-3-3-3 tor FPM.
The DRAM interface supports 4 Mbytes to 256 Mbytes with six RAS
lines. The MTXC supports 4-Mbit, 16-Mbit, and 64-Mbit DRAM and SDRAM
technology. both symmetrical and asymmetrical. Parity is not
supported, and for loading reasons, x32 and x64 SIMMs/DlMMs/SO-DIMMs
should be used.
Second Level Cache
The second level cache is direct mapped and supports both 256-Kbyte
and 512-Kbyte SRAM configuration using Pipeline Burst SRAM or DRAM
Cache SRAM. The Cache performance is 3-1-1-1 for line read/write and
3-1-1-1-1-1-1-1 for back to back reads that are pipelined. Cacheless
configuration is also supported.
PCI Interface
The PCI interface is 2.1 compliant and supports up to four PCI bus
masters in addition to the PIIX4 bus master requests.
Datapath and Buffers
The MTXC contains three sets of data buffers for optimizing data
flow. A five QWord deep DRAM write buffer is provided for CPU-to-DRAM
writes, second level cache write backs, and PCI-to-DRAM
transfers. This buffer is used to achieve 3-1-1-1 posted writes to
DRAM and also provides DWord merging and burst merging for CPU-to-DRAM
write cycles. In addition, an extra line of buffering is provided that
is combined with the DRAM Write Buffer to supply an 18 DWord deep
buffer for PCI to main memory writes. A five DWord buffer is provided
for CPU-to-PCI writes to help maximize the bandwidth for graphic
writes to the PCI bus. Also, five QWords of prefetch buffering has
been added to the PCI-to-DRAM read path that allows up to two lines of
data to be prefetched at an x-2-2-2 rate. The MTXC interfaces directly
to the Host and DRAM data bus.
Power Management Features
The MTXC implements extensive power management features. The CLKRUN#
feature enables controlling of the PCI clock (on/off). The MTXC
supports POS. STR, STD, and Soft-off suspend states. SUSCLK and
SUSSTAT1# signals are used for implementing Suspend Logic. The MTXC
supports two SMRAM modes; Compatible SMRAM (C_SMRAM) and Extended
SMRAM (E_SMRAM). The C_SMRAM is the traditional SMRAM feature
implemented in Intel PCIsets. The E_SMRAM is a new feature that
supports writeback cacheable SMRAM space up to 1 Mbytes. In order to
minimize the idle power, the internal clock in MTXC is turned off
(gated off) when there is no activity on the Host and PCI Bus.
***Configurations:...
***Features:...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97
***Notes:...
***Info:...
***Versions:...
***Features:...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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