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*ACC Micro...
**Other chips
ACC1200   Clock synthesizer Supports Pentium-Pro and Pentium-class PCI
ACC16C451 Multi I/O 1x16450/1xLPT
ACC16C452 Multi I/O 2x16450/1xLPT
ACC16C461 Multi I/O 1x16450/1xLPT
ACC2042   Keyboard/Mouse Controller
ACC2188   PCI bus controller  Support 32-bit PCI Bus interface with built-in power management control and synchronous / asynchronous clock feature. 
ACC3201   PC/XT/AT FDD Controller
ACC3202   PS/2 FDD Controller
ACC3203   PS/2 FDD Controller
ACC3211   PC AT/XT FDD Controller (x4) + with IDE
ACC3221   Multi I/O Controller, floppy/IDE/2x16450/1xLPT
ACC3223   Multi I/O Controller, floppy/IDE/2x16550/1xLPT
ACC3350   Ultra SCSI 
ACC3360   UltraWide SCSI 
ACC3618   3D surround controller ISA
ACC5810   Micro Channel Interface Chip
ACC808 	  Plug-and-Play Controller
ACC????   Manhattan PCI-based FireWire for Pentium
ACC????   Memphis PCI-based CardBus and FireWire

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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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