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**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93
***Notes:...
***Info:
****All...
****Oct'93...
****Dec'94...
****All
1.0 ARCHITECTURAL OVERVIEW
The major functions of the SIO  component are broken up into blocks as
shown in the preceding figure  [see datasheet].  A description of each
block is provided below.

PCI Bus Interface:
The PCI Bus  Interface provides the interface between  the SIO and the
PCI bus. The SIO provides both a master and slave interface to the PCI
bus.  As a  PCI master,  the SIO  runs cycles  on behalf  of  DMA, ISA
masters,  and the internal  data buffer  management logic  when buffer
flushing is required. The SIO will  burst a maximum of two Dwords when
reading from PCI memory, and one Dword when writing to PCI memory. The
SIO does not generate PCI I/O cycles  as a master. As a PCI slave, the
SIO accepts  cycles initiated  by PCI masters  targeted for  the SIO's
internal register set or the ISA bus. The SIO will accept a maximum of
one data transaction before terminating the transaction. This supports
the  Incremental  Latency  Mechanism  as  defined  in  the  Peripheral
Component Interconnect (PCI) Specification.

As  a master,  the SIO  generates address  and command  signal (C/BE#)
parity for read and write cycles, and data parity for write cycles. As
a  slave, the  SIO  generates  data parity  for  read cycles.   Parity
checking is  not supported. The  SIO also provides support  for system
error  reporting  by generating  a  Non-Maskable-Interrupt (NMI)  when
SERR# is driven active.

The  SIO, as  a resource,  can be  locked by  any PCI  master.  In the
context of locked cycles, the  entire SIO subsystem (including the ISA
bus) is considered a single resource.

The SIO directly  supports the PCI Interface running  at either 25 Mhz
or  33 Mhz.  If  a frequency  of less  than  33 Mhz  is required  (not
including 25  Mhz), a  SYSCLK divisor value  (as indicated in  the ISA
Clock Divisor Register) must be  selected that guarantees that the ISA
bus frequency does not violate the 6 Mhz to 8.33 Mhz SYSCLK range.

PCI Arbiter: 
****Mar'93...
****Dec'94...
****All:...
***Versions:...
***Features:...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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