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**What's not included:
All  information included  in  this  file can  be  referenced to  some
document or  picture.  Or at least  should be:-) As a  result of this,
proprietary chip sets, and odd combinations of different chip sets are
not  usually  included.   There  tends  to  be  scant  information  on
proprietary chip sets, i.e.  no  datasheet.  Similarly chip sets built
using some components  from one manufacture and some  from another are
kind of difficult to deal with.

An example  I know of  is a  25 MHz 386  DX motherboard that  uses the
Intel N82230/N82231  (formerly, ZyMOS)  286 chip  set, with  an AUStek
cache Controller.   I know it  existed but there is  no documentation.
So the best I can say you'll have  to take my word that it existed.  I
can't include it because there is no real information there.

Also  not  included  is  anything  that  isn't  a  PC-compatible  chip
set.  I.e.  no Macintosh  info.  Any Information  on PC-incompatibles/
pseudo-compatibles, and  other weirdi-type  stuff I have  a particular
interest in.  See  the section: 'Info needed on'.  Some information on
video  chip  sets  is  included,  occasionally but  the  focus  is  on
motherboard implementation.

**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5595       Pentium PCI System I/O                          <12/24/97
***Notes:...
***Info:...
***Versions:...
***Features:...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...