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**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?
***Info:...
***Configurations:...
***Features:
****M1541/1542 AGP/CPU-to-PCI bridge/Memory/Cache and Buffer Ctrl.:
[The datasheet has some features shaded. These are represented below]
[by features enclosed in []. The datasheet does not explicitly state]
[these features only apply to the M1542, and are absent in the M1541.]
[However this is the most likely reason they are shaded. ]
o Supports all Socket 7 processors. Host bus at 100MHz, 83.3MHz,
75MHz, 66 MHz, 60 MHz and 50MHz at 3.3V/2.5V.
- Supports linear wrap mode for Cyrix M1 & M2
- Supports Write Allocation feature for K6
- Supports Pseudo Synchronous AGP and PCI bus access
(CPU bus 75MHz - AGP bus 60MHz, PCI bus 30MHz,
CPU bus 83.3MHz - AGP bus 66MHz, PCI bus 33MHz,
CPU bus 100MHz - AGP bus 66MHz, PCI bus 33MHz)
o Supports Pipelined-Burst SRAM/Memory Cache
- Direct mapped, 256KB/512KB/1MB
- Write-Back/Dynamic-Write-Back cache policy
- Built-in 16K*2 bit SRAM for MESI protocol to reduce cost and
enhance performance
[- Built-in 16K*10 bit SRAM for TAG data to reduce cost and ]
[ enhance performance (reserved) ]
- Cacheable memory up to 128MB with 8-bit Tag SRAM when using
512KB L2 cache, 256MB when using 256KB L2 cache.
- Cacheable memory up to 512MB with 10-bit Tag SRAM when using
512KB L2 cache, 1GB when using 256KB L2 cache
- 3-1-1-1-1-1-1-1 for Pipelined Burst SRAM/ Memory Cache at
back-to-back burst read and write cycles.
- Supports 3.3V/5V SRAMs for Tag Address.
- Supports CPU Single Read Cycle L2 Allocation.
o Supports FPM/EDO/SDRAM DRAMs
- 8 RAS Lines up to 4G Byte support
- 64-bit data path to Memory
- Symmetrical/Asymmetrical DRAMs
- 3.3V or 5V DRAMs
- No buffer needed for RASJ and CASJ and MA
- CBR and RAS-only refresh for FPM
- CBR and RAS-only refresh and Extended refresh and self refresh
for EDO
- CBR and Self refresh for SDRAM
- 32 QWORD deep merging buffer for 3-1-1-1-1-1-1-1 posted write
cycle to enhance high speed CPU burst access
- 6-3-3-3-3-3-3-3 for back-to-back FPM read page hit
5-2-2-2-2-2-2-2 for back-to-back EDO read page hit
6-1-1-1-1-1-1-1 for back-to-back SDRAM read page hit
X-2-2-2-2-2-2-2 for retired data for posted write on FPM and
EDO page-hit
X-1-1-1-1-1-1-1 for retired data for posted write SDRAM page-hit
- Supports SDRAM internal bank operation
- Enhanced DRAM page miss performance
- Supports 64, 128, 256M-bit technology of DRAMs
- Supports Programmable-strength CAS//MA buffers.
- Supports Error Checking & Correction (ECC
[ at or below 83.3 MHz only) and Parity for DRAM ]
- Supports 4 single-sided DIMMs based on x4 DRAMs
- Supports 4 single and double-sided DIMMs based on x8 and x16
DRAMs
- Supports 4 single-sided registered DIMMs based on 4 bits data
width SDRAM
o Synchronous/Pseudo Synchronous 25/30/33MHz 3.3V/5V tolerance PCI
interface
- Concurrent PCI architecture
- PCI bus arbiter: Five PCI masters and M1533/M1543 (ISA Bridge)
and AGP Master supported
- 6 DWORDs for CPU-to-PCI Memory write posted buffers
- Converts back-to-back CPU to PCI memory write to PCI burst cycle
- 80/22 DWORDs for PCI-to-DRAM Write-posted/Read-prefetching
buffers
- PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write
back)
- L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle
- Supports PCI mechanism #1 only
- PCI spec. 2.1 support. (N(32/16/8)+8 rule, passive release, fair
arbitration)
- Enhanced performance for Memory-Read-Line and Memory-Read-
Multiple and Memory-write-Invalidate PCI commands.
o Enhanced Power Management
- ACPI support
- Supports PCI bus CLKRUN function
- Supports Dynamic Clock Stop
- Supports Power On Suspend
- Supports Suspend to Disk
- Supports Suspend to DRAM
- Self Refresh during Suspend
o Accelerated Graphics Port (AGP) Interface
- Supports AGP specification V1.0
- Supports up to 64 entries table look aside buffer for Graphic
Address Remapping Table (GART)
- AGP 66MHz protocol
- AGP 1X and 2X sideband address function
- 28 entries Request queue
- 32 QWORDs Read buffer
- 16 QWORDs Write buffer
o 35x35 mm 456-pin BGA package
****M1543/C PCI-to-ISA Bus Bridge with Super I/O & Fast IR:...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**8289 Bus Arbiter (808x) c79
***Notes:...
***Info:...
***Versions:...
***Features:...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
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