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**M????          Genie, Quad Pentium  [no datasheet, some info]    c95
***Notes:...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
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**Support Chips:
**M1535/D        South Bridge                                        ?...
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*AMD . . . . . . . [no datasheets, some info]...
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*Intel...
**82430HX     PCIset (Pentium) HX (Triton II) (82439HX)       02/12/96
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430VX     PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96
***Notes:...
***Info:
The  Intel 430VX  PCIset  consists of  the  82437VX System  Controller
(TVX), two  82438VX Data Paths (TDX),  and the PCI  ISA IDE Xcelerator
(PIIXS).  The PCIset  forms  a Host-to-PCI  bridge  and  provides  the
second level  cache control  and a full  function 64-bit data  path to
main memory. The TVX integrates the cache and main memory DRAM control
functions  and provides  bus control  for transfers  between  the CPU,
cache,  main memory,  and the  PCI Bus.  The second  level  (L2) cache
controller supports a  write-back cache policy for cache  sizes of 256
Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache
memory  can be  implemented with  standard, pipelined  burst,  or DRAM
Cache SRAMs.  An external Tag RAM is  used for the address  tag and an
internal Tag  RAM for the cache  line status bits. For  the TVX's DRAM
controller,  five rows  are supported  for up  to 128  Mbytes  of main
memory. The Shared Memory  Buffer Architecture (SMBA) 2-wire interface
allows a  graphics controller to use  an area of system  memory as its
frame  buffer.  The  Intel  430VX  PCIset has  been  enhanced  through
additional buffers,  programmable timers, and burst  and DWord merging
and optimized  DRAM timings  to maintain a  high level  of performance
when used  in a SMBA environment.  Using the snoop  ahead feature, the
TVX allows PCI masters to achieve full PCI bandwidth. The TDXs provide
the  data paths  between  the  CPU/cache, main  memory,  and PCI.  For
increased  system  performance. the  TDXs  contain  read prefetch  and
posted write buffers.

1.0. ARCHITECTURE OVERVIEW OF TSC/TDP

The  Intel 430VX  PCIset (Figure  1) [see  datasheet] consists  of the
82437VX System  Controller (TVX), two  82438VX Data Path  (TDX) units,
and the PCI  IDE ISA Xcelerator (PIIXS).  The TVX and  two TDXs form a
Host-to-PCI  bridge.   The  PIIX3   is  a  multi-function  PCI  device
providing  a  PCI-to-ISA  bridge,   a  fast  IDE  interface,  an  APIC
interface,  and a  host/hub controller  for the  Universal  Serial Bus
(USB). The PIIX3 also provides power management.

The two TDXs provide a 64-bit data path to the host and to main memory
and provide a 16-bit data path  (PLINK) between the TVX and TDX. PLINK
provides the  data path for  CPU to PCI  accesses and for PCI  to main
memory accesses.  The  TVX and TDX bus interfaces  are designed for 3V
and 5V busses. The Intel 430VX PCIset connects directly to the Pentium
processor 3V host bus; The  Intel 430VX PCIset connects directly to 5V
or 3V main  memory DRAMs; and the TVX connects directly  to the 5V PCI
Bus.

The  TVX and  TDX interface  with the  Pentium processor  host  bus, a
dedicated memory  data bus,  and the PCI  bus. The Intel  430VX PCIset
implements a Shared Memory Buffer Architecture (SMBA) handshake 2-wire
protocol that allows a graphics  controller to use a portion of system
memory as its frame buffer region.  In addition, the PLINK bus is used
to  connect the  PCI bus  with the  TDX, through  the TVX  (see Figure
1). [see datasheet]

DRAM Interface
The DRAM interface  is a 64-bit data path  that supports Standard Page
Mode  (SPM), Extended  Data Out  (EDO), and  Synchronous  DRAM (SDRAM)
memory. The DRAM  interface supports 4 Mbytes to  128 Mbytes of system
memory  with  five  RAS   lines  and  also  supports  symmetrical  and
asymmetrical addressing for 512Kx32, 1Mx32, 2Mx32, and 4Mx32 deep SIMM
modules  (single- and  double-sided).  The TVX  supports SDRAM  1Mx64,
2Mx64,  and   4Mx64  deep  DIMM  modules   (asymmetrical  single-  and
double-sided).  The Intel  430VX PCIset  does not  support  parity and
requires that x32 and x64 SIMMs/DIMMs be used.

Second Level Cache
The  TVX supports a  write-back cache  policy providing  all necessary
snoop functions and  inquire cycles. The second level  cache is direct
mapped and  supports both a 256-Kbyte or  512-Kbyte SRAM configuration
using pipelined burst, DRAM Cache,  or standard SRAMs. DRAM Cache is a
DRAM based cache  alternative to pipelined burst SRAM.  Its pinout is a
superset of pipeline burst and conforms to the standard pipeline burst
footprint. One  chipset signal (KRQAK), two system  signals (H/WR# and
RESET#), and one DRAM Cache specific signal (M/S#) are the only signal
differences between pipeline burst SRAM and DRAM Cache. The Pipeline
burst  or   DRAM  Cache  configuration  performance   is  3-1-1-1  for
read/write cycles;  back-to-back reads can  maintain a 3-1-1-1-1-1-1-1
transfer rate.

TDX
Two TDXs create a 64-bit CPU memory data path. The TDXs also interface
to  the  16-bit  PLINK  inter-chip  bus  on  the  TVX  for  PCI  tran-
sactions. The  combination of  the 64-bit memory  path and  the 16-bit
PLINK bus make  the TDXs a cost effective  solution, providing optimal
CPU-to-main  memory  performance, while  maintaining  a small  package
footprint (100 pins each).

PCI Interface
The PCI  interface is 2.1  compliant and supports  up to four  PCI bus
masters in addition to the PIIX3 bus master requests. The TVX and TDXs
together  provide   the  interface   between  PCI  and   main  memory;
however only the TVX connects to the PCI bus.

Buffers
The TVX and TDXs together contain three sets of buffers for Optimizing
data  flow. A  DRAM write  buffer is  provided for  CPU-to-main memory
writes, second  level cache write-back cycles,  and PCI-to-main memory
transfers. This  buffer is  used to achieve  3-1-1-1 posted  writes to
main memory, and also provides DWord merging and burst merging for CPU
to  main memory write  cycles. Buffering  is provided  for PCI-to-main
memory writes. A buffer is  provided for CPU-to-PCI writes to maximize
the  bandwidth  for  graphic writes  to  the  PCI  bus in  a  non-SMBA
system.  In  addition,  PCI-to-main  memory read  pre-fetch  buffering
permits up to two lines of data to be prefetched at an x-2-2-2 rate.

Shared Memory Buffer Architecture (SMBA)
The Intel  430VX PCIset  provides a hardware  interface that  allows a
graphics  controller to access  an area  of system  memory as  a frame
buffer.  This reduces  system cost  by  eliminating the  need to  have
separate memory  for the graphics  subsystem. Two signals are  used to
arbitrate ownership  of DRAM (DRAM  address and control  signals). The
Intel 430VX  PCIset has  been enhanced as  follows to maintain  a high
level of performance when used in a SMBA environment:

o  Buffering for improved CPU and PCI posting and PCI pre-fetching
o  Programmable timers to maximize performance and establish a balance 
   between the graphics/controller and the system (regulates read  and 
   write accesses to DRAM)
o  Burst merging and DWord merging for efficient DRAM writes
o  Optimized DRAM Read timings

System Clocking
The processor,  secondary cache, main memory subsystem,  and PLINK bus
all run  synchronously to the  host clock. The host  clock frequencies
supported  are  50  MHz, 60  MHz.  and  66  MHz.  The PCI  clock  runs
synchronously at half the host  clock frequency. The TVX and TDXs have
a host  clock input and  the TVX has  a PCI clock input.  These clocks
come from an external source and have a maximum clock skew requirement
with respect to each other.


***Configurations:...
***Features:...
**82430TX     PCIset (Pentium) TX (Triton II) (82439TX)       02/17/97...
**82450KX/GX  PCIset (Pentium Pro) KX/GX (Mars/Orion)         11/01/95...
**
**Support Chips:
**82091AA     Advanced Interface Peripheral (AIP)                  c93...
**8289        Bus Arbiter (808x)                                   c79...
**82289       Bus Arbiter for iAPX 286 Processor Family            c83...
**82258       Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335       High-Integration Interface Device For 386SX      c:Nov88...
**82360SL     I/O Subsystem                                   10/05/90...
**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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