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**82420EX     PCIset (for 486) EX (Aries)   (82425EX/82426EX)   <Dec94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82430LX     PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX     PCIset (Pentium) NX (Neptune) (82433NX/82434NX)    Mar94...
**82430FX     PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX     PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX     PCIset (Pentium) HX (Triton II) (82439HX)       02/12/96
***Notes:...
***Info:
The Intel 430HX PCIset consists of the 82439HX System Controller (TXC)
and  the  82371SB  PCI  I/O  IDE  Xcelerator (PIIX3).  The  TXC  is  a
single-chip host-to-PCI  bridge and  provides the second  level cache
control  and  DRAM control  functions.  The  second  level (L2)  cache
controller supports a  write-back cache policy for cache  sizes of 256
Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache
memory  is  implemented with  synchronous  pipelined  burst SRAMs.  An
external Tag RAM  is used for the address tag and  an internal Tag RAM
for the cache line status bits. The TXC provides a 64/72-bit data path
to main memory and memory sizes  up to 512 Mbytes. The DRAM controller
provides eight  rows and  optional DRAM Error  detection/correction or
parity. The  TXC‘s optimized PCI  interface allows the CPU  to sustain
the highest  possible bandwidth  to the graphics  frame buffer  at all
frequencies. Using the snoop ahead feature, The TXC allows PCI masters
to achieve  full PCI bandwidth. For increased  system performance, the
TXC contains read prefetch and posted write buffers.

1.0. ARCHITECTURE OVERVIEW
The TXC  interfaces with the  Pentium processor host bus,  a dedicated
memory data bus,  and the PCI bus (Figure 1)  [see datasheet]. The TXC
connects directly to the Pentium processor 3V host bus, directly to 5V
or 3V DRAMs.   and directly to the 5V PCI bus.  The Intel 430HX PCIset
consists of  the 82439HX TXC  and the PCI IDE/ISA  Xcellerator (PIIXS)
components. PIIXS provides the  PCI-to-ISA bridge functions along with
other features  such as a  fast IDE interface, Plug'n-Play  port, APIC
interface,  Universal   Serial  Bus  (USB)  and   PCI  2.1  Compliance
operation.

Data Flow
Processor  cycles are  sent directly  to the  second level  cache with
control  for the second  level cache  provided by  the TXC.  All other
processor cycles are sent to  their destination (DRAM, PCI or internal
TXC configuration  space) via the TXC.  PCI Master cycles  are sent to
main memory through the TXC.  The TXC performs snoop or inquire cycles
using the host bus.

DRAM Interface
The  DRAM  interface is  a  64/72-bit  data  path that  supports  both
standard  page mode  and  Extended  Data Out  (EDO)  memory. The  DRAM
interface supports  4 Mbytes to 512  Mbytes with 8 RAS  lines and also
supports symmetrical  and asymmetrical addressing  for 1M, 2M,  and 4M
deep SIMMs and symmetrical addressing for 16-Mbyte deep SIMMs.

Second Level Cache
The  TXC supports a  write-back cache  policy providing  all necessary
snoop functions and  inquire cycles. The second level  cache is direct
mapped and  supports both a 256-Kbyte or  512-Kbyte SRAM configuration
using  pipelined  burst   SRAMs.  The  burst  256-Kbyte  configuration
performance is  3-1-1-1 for read/write  cycles; pipelined back-to-back
reads can  maintain a 3-1-1-1-1-1-1-1 transfer rate.  An optional mode
extends the DRAM L2 cacheability range to 512 Mbytes.

PCI Interface
The  PCI interface  is 2.1  compliant  and supports  up to  4 PCI  bus
masters in addition to the  PIIX3 bus master requests. The PCI-to-DRAM
interface can  reach a 112 Mbyte/sec  transfer rate for  reads and 121
Mbytes/sec for writes.

Data Path and Buffers
The  TXC  data path  is  optimized  for  minimum latency  and  maximum
throughput  operation from  both  the  CPU and  PCI  masters. The  TXC
contains  two physical  sets of  buffers for  optimizing data  flow. A
6-DWord buffer  is provided for CPU-to-PCI writes  that helps maximize
the graphic  writes to PCI  bandwidth. An 8-QWord deep  merging memory
buffer  is  provided  that  is  used for  CPU-to-main  memory  writes,
write-back   cycles  (Posted  at   3111),  PCI-to-main   memory  write
posting. and PCI-from-main memory read prefetching.

Error Detection and Correction
Parity or  error correction are software  configurable options (parity
is  the  default).  The  ECC mode  provides  single-error  correction,
double-error  detection, and  detection of  all errors  confined  to a
single nibble for the DRAM memory subsystem.

***Configurations:...
***Features:...
**82430VX     PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX     PCIset (Pentium) TX (Triton II) (82439TX)       02/17/97...
**82450KX/GX  PCIset (Pentium Pro) KX/GX (Mars/Orion)         11/01/95...
**
**Support Chips:
**82091AA     Advanced Interface Peripheral (AIP)                  c93...
**8289        Bus Arbiter (808x)                                   c79...
**82289       Bus Arbiter for iAPX 286 Processor Family            c83...
**82258       Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335       High-Integration Interface Device For 386SX      c:Nov88...
**82360SL     I/O Subsystem                                   10/05/90...
**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C360   'Haydn' 80386DX/SX chipset [no datasheet]         c:Jun91
***Notes:...
***Configurations:...
**SL82C460   'Haydn II' 80486 chipset   [no datasheet]         c:Jun91...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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