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**Definition of a chip set:
In short it is a set of  chips that allow a system designer to build a
computer.  If we restrict the term  'chip' to that of a microchip then
technically any microcomputer  contains a chip set, even  one based of
7400-series logic alone.

In the context of this document, a chip set is defined as any group of
chips used to implement  an IBM or IBM-compatible PC/XT/AT/386/486/etc
system.

There are 2 main categories that these chips fall into:
1. Direct copies or re-implementations of Intel chips
2. Chip sets sold as a set of chips to implement an IBM-compatible 
   that differ in some way to those used in an IBM system, e.g. not 
   pin compatible.

An  example of  the former  would be  some early  chips built  by VLSI
Technology (at the time known as VTI, to implement a 286:
o  VL82C37A is a: 82C37A DMA controller
o  VL82C59A is a: 82C59A interrupt controller
o  VL82C54A is a: 82C54 timer
o  VL82C612 is a: 74LS612 memory mapper
o  VL82C84A is a: 82284 clock generator and ready interface
o  VL82C88  is a: 82288 bus controller

These are  all direct replacements  for the parts  used in an  IBM AT.
Many companies had compatible versions of these chips.

An early example of the latter is the Chips & Technology NEAT chip set:
o  82C211 CPU/Bus controller, 
o  82C212 Page/Interleave and EMS Memory controller, 
o  82C215 Data/Address buffer 
o  82C206 Integrated Peripherals Controller (IPC).

The description does not map directly to the parts used in the IBM AT.
Later chip sets are often even more integrated sometimes consisting of
just one chip, although two seems to be the most common.

The latter  is generally considered  the definition of a  chip set, and
the former is not generally  considered a chip set per-se. However when
looking  at   the  early  chip sets   this  distinction  can   be  very
slight. Because of this,  sets of chips  meeting the criteria  for (1.)
have been included where possible. 

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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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