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**82485       Turbo Cache (and 485Turbocache)                      c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97
***Info:...
***Versions:...
***Features:
o   Support Intel Pentium CPU and other compatible CPU host bus 
    at 50/55/60/66/75 MHz
o   Support the Pipelined Address Mode of Pentium CPU
o   Support the Full 64-bit Pentium Processor data Bus
o   Meet PC97 Requirements
o   Integrated Second Level (L2) Cache Controller
    - Write Back/Write Through Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Integrated 16K bits Dirty RAM
    - Support Pipelined Burst SRAM
    - Support 256 KBytes and 512 KBytes Cache Sizes
    - Cache Hit Read/Write Cycle of 3-1-1-1
    - Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
o   Integrated DRAM Controller
    - Support 6/3 Banks (Single/Double sided) of FPM/EDO/SDRAM 
      DIMMs/SIMMs
    - Support 2Mbytes to 384Mbytes of main memory
    - Support Cacheable DRAM Sizes up to 128 MBytes.
    - Support 256K/512K/1M/2M/4M/8M/16M/32M x N FPM/EDO/SDRAM DRAM
    - Support 64 Mb DRAM Technology
    - Support 3.3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Support 32 bits/64 bits mixed mode configuration
    - Support Concurrent Write Back
    - Support CAS before RAS Refresh
    - Support Relocation of System Management Memory
    - Programmable CAS#, RAS# and MA Driving Current, No Glue TTL 
      need in 2 banks (up to 64MB) configuration.
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    - Support FPM DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
    - Support EDO DRAM 5-2-2-2(-2-2-2-2) Burst Read Cycles
    - Support SDRAM 6-1-1-1(-2-1-1-1) Burst Read Cycles
    - Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
    - Support 8 Qword Deep Buffer for Read/Write Reordering, Dword 
      Merging and 3/2-1-1-1 Post write Cycles
    - Two Programmable Non-Cacheable Regions
    - Option to Disable Local Memory in Non-Cacheable Regions
    - Shadow RAM in Increments of 16 KBytes
o   Integrated PMU Controller
    - Meet ACPI Requirements
    - Support Both ACPI and Legacy PMU
    - Support Suspend to Disk
    - Support SMM Mode of CPU
    - Support CPU Stop Clock
    - Support Power Button
    - Support Automatic Power Control
    - Support Battery Management AC Indicator and LB,LLB
    - Support Modem Ring-in, RTC Alarm Wake up
    - Support Thermal Detection
    - Support GPIOs, and GPOs for External Devices Control
    - Support Two Programmable Chip Select
o   Provides High Performance PCI Arbiter.
    - Support up to 5 PCI Masters
    - Support Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Support Concurrency between CPU to Memory and PCI to PCI.
    - Support Concurrency between CPU to L2 Cache and PCI/ISA to DRAM.
o   Integrated Host-to-PCI Bridge
    - Support Asynchronous and Synchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles
    - Zero Wait State Burst Cycles
    - Support IDE Posted Write
    - Support Pipelined Process in CPU-to-PCI Access
    - Support Advance Snooping for PCI Master Bursting
    - Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory.
    - CPU-to-Memory Read Buffer with 4 QW Deep
    - CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
    - PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o   Integrated PCI-to-ISA Bridge
    - Translates PCI Bus Cycles into ISA Bus Cycles
    - Translates ISA Master or DMA Cycles into PCI Bus Cycles
    - Provides a Dword Post Buffer for PCI to ISA Memory cycles
    - Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master 
      Performance
    - Fully Compliant to PCI 2.1
o   Enhanced DMA Functions
    - 8-, 16- bit DMA Data Transfer
    - ISA compatible, and Fast Type F DMA Cycles
    - Two 8237A Compatible DMA Controllers with Seven Independent 
      Programmable Channels
    - Provides the Readability of the two 8237 Associated Registers
    - Support Distributed DMA
o   Built-in Two 8259A Interrupt Controllers
    - 14 Independently Programmable Channels for Level- or Edge-
      triggered Interrupts
    - Provides the Readability of the two 8259A Associated Registers
    - Support Serial IRQ
o   Three Programmable 16-bit Counters compatible with 8254
    - System Timer Interrupt
    - Generates Refresh Request
    - Speaker Tone Output
    - Provides the Readability of the 8254 Associated Registers
o   Built-in Real Time Clock(RTC) with 256B CMOS SRAM
    - Built-in up to one Month Alarm for ACPI
o   Fast PCI IDE Master/Slave Controller
    - Bus Master Programming Interface for ATA Windows 95 Compliant 
      Controller
    - Support PCI Bus Mastering
    - Plug and Play Compatible
    - Support Scatter and Gather
    - Support Dual Mode Operation - Native Mode and Compatibility 
      Mode
    - Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
    - Support Multiword DMA Mode 0, 1, 2
    - Support Ultra DMA/33
    - Two Separate IDE Bus
    - Two 16 Dword FIFO for PCI Burst Transfers.
o   Universal Serial Bus Host Controller
    - OpenHCI Host Controller with Root Hub
    - Two USB ports
    - Support Legacy Devices
    - Support Over Current Detection
o   Support I2C Serial Bus
o   Support the Reroutibilty of the four PCI Interrupts
o   Support 2MB Flash ROM Interface
o   Support NAND Tree for ball connectivity testing
o   480-Balls BGA Package
o   0.35μm 3.3V Technology

**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97
***Notes:...
***Info:...
***Versions:...
***Features:...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
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