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*Contaq  . . . . . [no datasheets, some info]...
**82C599    PCI-VLB Bridge [no datasheet, some info]                 ?

82C599 PCI-VLB Bridge referenced in:
http://web.mit.edu/netbsd/src/sys/dev/pci/pcidevs

from:
https://web.archive.org/web/20050313090427/http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html

"The Contaq Chipset (Contaq: 1080/4224) (8/27/95)

The Contaq 82C599  is paired with one of  their 486VL chipsets (82C596
or  82C597) and  bridges directly  from the  486 CPU  to the  PCI bus.
Paraphrased from the Contaq spec.:

The  82C596 system  controller provides  the CPU  interface,  VESA bus
interface, ISA bus controller, etc. The 82C599 PCI controller provides
the bridge  between PCI master/slave  agent and the  ISA/VESA standard
expansion  bus; it arbitrates  all the  bus transactions  between host
CPU, PCI agent, VESA device, and ISA device.

(Which sounds to me like the PCI bus is attached to the VL bus, rather
than to the CPU, which will cause PCI performance degradation.)"

**82C693    PCI-ISA Bridge [no datasheet]                            ?...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*Unresearched:...
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*General Sources:...