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**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97
***Info:...
***Configurations:...
***Features:
****M1531 CPU-to-PCI bridge, Memory, Cache and Buffer Controller:
o   Supports all Intel/Cyrix/AMD/TI/IBM 586 socket processors. Host 
    bus at 83.3MHz, 75MHz, 66 MHz, 60 MHz and 50MHz at 3.3V/2.5V.
    - Supports linear wrap mode for Cyrix M1 & M2
    - Supports Write Allocation feature for K6
    - Supports Pseudo Synchronous PCI bus access 
      (CPU bus 75MHz - PCI bus 30MHz,
       CPU bus 83.3MHz - PCI bus 33MHz)
o   Supports Pipelined-Burst SRAM
    - Direct mapped, 256KB/512KB/1MB
    - Write-Back/Dynamic-Write-Back cache policy
    - Built-in 8K*2 bit SRAM for MESI protocol to reduce cost and 
      enhance performance
    - Cacheable memory up to 64MB with 8-bit Tag SRAM
    - Cacheable memory up to 512MB with 11-bit Tag SRAM
    - 3-1-1-1-1-1-1-1 for Pipelined Burst SRAM at back-to-back burst 
      read and write cycles.
    - Supports 3.3V/5V SRAMs for Tag Address.
    - Supports CPU Single Read Cycle L2 Allocation.
o   Supports FPM/EDO/SDRAM DRAMs
    - 8 RAS Lines up to 1GByte support
    - 64-bit data path to Memory
    - Symmetrical/Asymmetrical DRAMs
    - 3.3V or 5V DRAMs
    - Duplicated MA[1:0] driving pins for burst access
    - No buffer needed for RASJ and CASJ and MA[1:0]
    - CBR and RAS-only refresh for FPM
    - CBR and RAS-only refresh and Extended refresh and self refresh 
      for EDO
    - CBR and Self refresh for SDRAM
    - 16 QWORD deep merging buffer for 3-1-1-1-1-1-1-1 posted write 
      cycle to enhance high speed CPU burst access
    - 6-3-3-3-3-3-3-3 for back-to-back FPM read page hit
      5-2-2-2-2-2-2-2 for back-to-back EDO read page hit
      6-1-1-1-2-1-1-1 for back-to-back SDRAM read page hit
      2-2-2-2 for retired data for posted write on FPM and EDO 
      page-hit
      x-1-1-1 for retired data for posted write SDRAM page-hit
    - Enhanced DRAM page miss performance
    - Supports 64M-bit (16M*4, 8M*8, 4M*16) technology of DRAMs
    - Supports Programmable-strength RAS/CAS/MWEJ/MA buffers.
    - Supports Error Checking & Correction (ECC) and Parity for DRAM
    - Supports the most flexible six 32-bit populated banks of DRAM to 
      support the most friendly DRAM upgrade ability [you can tell 
      marketing got a hold of this datasheet]
    - Supports SIMM and DIMM
o   Synchronous/Pseudo Synchronous 25/30/33MHz 3.3V/5V tolerance PCI 
    interface
    - Concurrent PCI architecture
    - PCI bus arbiter: five PCI masters and M1533/M1543 (ISA Bridge) 
      supported
    - 6 DWORDs for CPU-to-PCI Memory write posted buffers
    - Converts back-to-back CPU to PCI memory write to PCI burst cycle
    - 38/22 DWORDs for PCI-to-DRAM Write-posted/Read-prefetching 
      buffers
    - PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 
      writeback)
    - L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle
    - Supports PCI mechanism #1 only
    - PCI spec. 2.1 support. (N(32/16/8)+8 rule, passive release, fair 
      arbitration)
    - Enhanced performance for Memory-Read-Line and Memory-Read-
      Multiple and Memory-write-Invalidate PCI commands.
o   Enhanced Power Management
    - ACPI support
    - Supports PCI bus CLKRUN function
    - Supports Dynamic Clock Stop
    - Supports Power On Suspend
    - Supports Suspend to Disk
    - Supports Suspend to DRAM
    - Self Refresh during Suspend
o   328-pin (27mmx27mm) BGA package

****M1533 PCI-to-ISA Bus Bridge:...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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