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**82C601/A Single Chip Peripheral Controller                 <08/30/90
***Notes:...
***Info:
The 82C601 single chip peripheral controllers is the second generation
of our Multifunction Controller product line.

This  chip  is  an  LSI  implementation  of  the  most  commonly  used
peripheral devices found in an IBM PC,  XT or AT. The chip features 16
mA  drivers for  the output  buffers, such  as the  host data  bus and
parallel port  data bus. It  incorporates two 16450  compatible UARTs,
one enhanced  parallel port (with bi-directional  capability), and IDE
compatible  hard  disk interface  and  various  chip selects  (in  the
MOTHERBOARD Application) or select pins  and Game port decodes (in the
ADAPTER Application).  Decoding logic  and support for main, auxiliary
and standby  power supplies  and software configurable  base addresses
for  these   devices,  operational  modes  and   interrupts  are  also
included. This chip supports 2 applications:

MOTHERBOARD  Application  where all  the  ports  are relocatable.   An
Integrated  Drive  electronics  Interface, and  various  Chip  Selects
(Floppy Disk, Real  Time Clock and a General Purpose)  have been added
for  this  mode.   Power  management  aspects of  the  82C601  in  the
MOTHERBOARD  Application  include  modular power  down  through  PWRGD
pin. When the  chip is powered down (i.e. when  PWRGD is inactive) the
current draw  should be less  than 50  micro-Amps, all the  inputs are
disabled, and  all outputs  are tri-stated.  the  contents of  all the
registers are  preserved, as  long as  power supply  to the  82C601 is
maintained.

ADAPTER  Application  where  the  base   address  for  the  ports  are
determined by the select pins (PSPz,  SSPs, ASPs, and PPS); except for
game port, it is fixed @  200H- 207H.  -GAMERD and -GAMEWR outputs are
provided to minimize external gate count.

The host  interface is PC  compatible, i.e. DO-D7, A0-A9,  -IOR, -IOW,
AEN,  INTR1, INTR2,  INTR3, INTR4,  and  RESET, and  can be  connected
directly  to the  bus. The  data buffers  (DO-D7, PD0-PD7,  IDED7) are
capable of sinking 16 mA @ 0.5v, the parallel port control signals are
open collector  with internal  pull up resistors;  and are  capable of
sinking 16 mA @ 0.5V.

The  UARTs  implement  fully  functional  serial  links.  Programmable
character length, parity generation and detection, stop-bit generation
and baud  rate generation  are provided. Double  buffering is  used so
that  precise synchronization  is unnecessary.  Status  information is
accessible  to the CPU  by reading  internal registers.  MODEM control
lines  are  provided, as  are  internal  diagnostic functionality  and
interrupt prioritization. Support for  an auxiliary power system (such
as that derived from a telephone line or RS232 link) permits an 82C601
in  a battery-powered  device to  consume  no battery  power until  an
incoming character is detected.

The  parallel  port  can   be  configured  for  output  only  (printer
application) or  input and output (bi-direction}.  

The  configuration   RAM  and  circuitry   support  programmable  base
addresses  for  all  registers  internal  to the  chip.  This  permits
creation of a menu-driven  program for system configuration. Selection
of  sources  for  interrupts;  enabling  and  configuring  of  on-chip
subsystems  (UARTS.   parallel  port.    etc.)  and  control   of  the
configuration process  itself are also  handled with this RAM  and its
associated circuitry.  The remainder  of this data sheet will consider
each  of the aforesaid  subsystems individually.   Sections containing
more general design data for the chip  as a whole are at the end along
with electrical and physical characteristics.

***Versions:...
***Features:...
**82C607   Multifunction Controller                             <Jun88
***Info:...
***Versions:...
***Features:...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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