; Olivetti 486/33 Primary CPU Board 1.1, Configuration File rev 1.02

BOARD
  ID = "OLI90C1"
  NAME = "Olivetti 486 Primary CPU Board Rev. 1.1"
  MFR = "OLIVETTI"
  CATEGORY = "CPU"
  SLOT = OTH, "PCPU"
  READID = NO
  AMPERAGE = 1000

IOPORT(1) = 0C90h		;Config Register 0
  INITVAL = 0000000xb		;Note: Bit 0 486 Internal Cache enable

IOPORT(2) = 0C91h		;Config Register 1
IOPORT(3) = 0C92h		;Status/ERROR Register 0
IOPORT(4) = 0C93h		;Status/ERROR Register 1
IOPORT(5) = 0C94h		;2nd Level CACHE Policy Register
  INITVAL = xxx10001b

IOPORT(6) = 0C95h		;ELCR for 8259 Controller #1
				;Note: This register has no effect.  The
				;      motherboard ELCR register is used.

IOPORT(7) = 0C96h		;ELCR for 8259 Controller #2
				;Note: This register has no effect.  The
				;      motherboard ELCR register is used.

IOPORT(8) = 0C97h		;CPU Diagnostic Register
IOPORT(9) = 0C70h		;CPU WHO-AM-I Register
IOPORT(10) = 0C6Ah		;CPU Control Port 0 Register
   INITVAL = 0000xx00b

IOPORT(11) = 0C88h		;Olibus Slot 0 secondary id byte register
IOPORT(12) = 0C89h		;Olibus Slot 0 secondary id byte register
IOPORT(13) = 0C8Ah		;Olibus Slot 0 secondary id byte register
IOPORT(14) = 0C8Bh		;Olibus Slot 0 secondary id byte register
IOPORT(15) = 0CA2h		;CPU Control Port 1 Register
IOPORT(16) = 0CB2h		;CPU Board Local Self-Test Results Register

;INCLUDE="OLILSXMP.OVL"
;BEGINOVL
FUNCTION = "Primary CPU Board"
  TYPE = "CPU,80486"
  CHOICE = "Present"

FUNCTION = "Reserved Memory"
   SHOW = NO
   CHOICE = "Present"
   combine
       MEMORY = 256K			;CPU Cache-ability SRAM
       ADDRESS = 0E0000000h
       WRITABLE = NO
       MEMTYPE = OTH
   combine
       MEMORY = 256K			;CPU Tag and Attribute RAM
       ADDRESS = 0F0780000h
       WRITABLE = NO
       MEMTYPE = OTH

FUNCTION = "Interprocessor IRQ"
   HELP = "The interprocessor interrupt is provided to allow Olibus-4 CPU
   card processors to interrupt each other.  This function is used when
   multiple CPU cards are installed in the system.  To take effect, the
   operating system must support this functionality."
   CHOICE = "IRQ 15"
      LINK
	IRQ	= 15
	SHARE	= YES
	TRIGGER = LEVEL
	INIT	= IOPORT(10) LOC(3 2) 00
   CHOICE = "IRQ 11"
      LINK
	IRQ	= 11
	SHARE	= YES
	TRIGGER = LEVEL
	INIT	= IOPORT(10) LOC(3 2) 01
   CHOICE = "IRQ 10"
      LINK
	IRQ	= 10
	SHARE	= YES
	TRIGGER = LEVEL
	INIT	= IOPORT(10) LOC(3 2) 10
   CHOICE = "Disabled"
      FREE
	INIT	= IOPORT(10) LOC(3 2) 11

FUNCTION = "CPU Diagnostic Serial Port"
  SHOW = NO
  CHOICE = "Com 6"
    link
      PORT = 0808h-080Fh	      ;Port initialization done by BIOS
;ENDOVL