;
; Altos M1 System Board Configuration File
;   EISA Product ID:
;     Product number   = 45
;     Revision level   = 1
;     EISA bus version = 1
;
;	This configuration file is a re-hash of !acs0709
;
BOARD
  ID       = "ACR4509"
  NAME     = "ACER/Altos M1 System Board"
  MFR      = "ACER/Altos Computer Systems"
  CATEGORY = "SYS"
  SLOT     = EMB(0)
  AMPERAGE = 2600
  READID   = YES
  IOCHECK  = INVALID
  COMMENTS = "This system board contains
	6 EISA slots and is capable of supporting 
	up to a maximum of 256MB memory.  A CPU expansion slot is
	provided for interchangable CPU boards.  Connectors for
	Keyboard and Mouse are standard.
	A floppy disk drive controller, an IDE
	interface, two asynchronous serial ports, and a parallel port
	are supplied as embedded devices on this board."

SYSTEM
  NONVOLATILE = 8192
  AMPERAGE    = 22000	;Amps available for expansion boards to use

; NOTE: The Physical slot number [SLOT(n)] to
;	Slot Specific I/O address [EISA(z)] feature
;	and the 'LABEL' statememt are not defined in EISA spec. V3.10,
;	but are supported by MCS's ECU

; EISA slots are by default BUSMASTER slots
  SLOT(1) = OTHER(15),"M1_CPU"       SKIRT = NO	LABEL = "CPU slot"
  SLOT(2) = EISA(6)   LENGTH = 341   SKIRT = NO	LABEL = "Slot 6"
  SLOT(3) = EISA(5)   LENGTH = 341   SKIRT = NO	LABEL = "Slot 5"
  SLOT(4) = EISA(4)   LENGTH = 341   SKIRT = NO	LABEL = "Slot 4"
  SLOT(5) = EISA(3)   LENGTH = 341   SKIRT = NO	LABEL = "Slot 3"
  SLOT(6) = EISA(2)   LENGTH = 341   SKIRT = NO	LABEL = "Slot 2"
  SLOT(7) = EISA(1)   LENGTH = 341   SKIRT = NO	LABEL = "Slot 1"

; Provide the system with a cache granularity map.
; NOTE: This optional feature is not defined in EISA spec. V3.10,
;	but is supported by MCS's ECU.

  MEMORY = 64M
    ADDRESS = 0h
    CACHE   = YES
    STEP    = 4k		;Cache granularity


IOPORT(1) = 022h		;LIO.E index register
  SIZE = BYTE
  INITVAL = xxxxxxxx

IOPORT(2) = 023h		;LIO.E data register
  SIZE = BYTE
  INITVAL = xxxxxxxx

IOPORT(3) = 0c60h		;D1 & 0 = INTR to CPU Filter/Latch control
  SIZE = BYTE			;D2 = access to enhanced COM functions
  INITVAL = 00000xxx


;;
SWITCH(1) = 4			;4 position DIP switch
  NAME     = "Feature Switch"
  STYPE    = DIP
  VERTICAL = YES
  REVERSE  = NO
  LABEL    = LOC(1-4) "spare" "Ignore" "Secure" "Reset"
  INITVAL  = LOC(1-4) 0001
  FACTORY  = LOC(1-4) 0001
  COMMENTS = "This switch block controls the following features:
\n  	Switch 1 - spare (leave in OFF position)
\n	Switch 2 - ON  = ignore EISA CMOS during POST
\n		   OFF = apply EISA CMOS configuration data
\n	Switch 3 - ON  = BIOS Security Setup not accessible
\n		   OFF = Security setup thru BIOS accessible
\n	Switch 4 - ON  = Enable front panel Reset switch
\n		   OFF = Disable front panel Reset switch"

JUMPER(1) = 1
  NAME     = "E1"
  JTYPE    = INLINE
  VERTICAL = NO
  REVERSE  = NO
  LABEL	   = LOC(2 1) "Reset" "Enable"
  INITVAL  = LOC(2^1) 1
  FACTORY  = LOC(2^1) 1
  COMMENTS = "This jumper determines if the Front Panel Reset switch
  	can be disabled.  If this jumper is installed, the Keyboard Lock
	switch has no affect on the Front Panel Reset switch.  If this
	jumper is removed, then locking the keyboard will also disable
	the Front Panel Reset switch."
;;


FUNCTION = "System Memory"    
  TYPE     = "MEM"
  COMMENTS = "The amount of extended memory installed and the amount of
	base memory enabled can be independently set for this system."

  CHOICE   = "Extended and Base Memory"
	AMPERAGE   = 1600
	FREE
	MEMORY = 0M - 63M STEP = 1M
      		ADDRESS  = 1M
      		MEMTYPE  = SYS
      		WRITABLE = YES
      		CACHE    = YES
  		SHARE	 = NO
	FREE
	MEMORY = 640K | 576K | 512K | 448K | 384K | 320K | 256K
			;256K - 640K STEP = 64K
      		ADDRESS  = 0
      		MEMTYPE  = SYS
      		WRITABLE = YES
      		CACHE    = YES
  		SHARE	 = NO


FUNCTION = "Mouse port"
  TYPE     = "PTR,8042"
  COMMENTS = "The mouse port is a PS/2 compatible port."
  CONNECTION = "Standard PS/2 style DIN connector"

  CHOICE   = "Enabled"
	DISABLE = NO
	FREE
	IRQ = 12
		SHARE   = NO
		TRIGGER = EDGE

	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000001	;c1h
	INIT = PORTADR(23h) 0rrrrrrr	;Edge Mode Interrupt

	INIT = PORTADR(22h) 11000001	;c1h
	INIT = PORTADR(23h) r1rrrrrr	;Enable Mouse Interrupt

	PORT = 60h - 64h
		SHARE = "8042"
		SIZE = BYTE

  CHOICE   = "Disabled"
	DISABLE = YES
	FREE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000001	;c1h
	INIT = PORTADR(23h) r0rrrrrr	;Disable Mouse Interrupt


FUNCTION = "Keyboard port"
	TYPE = "KEY,8042"
	COMMENTS = "PS/2 compatible keyboard"
	CONNECTION = "Standard PS/2 style DIN connector"
	HELP	= "The installed keyboard must be set to send 'PS/2' or 
	'AT' style key codes."

	CHOICE = "Enabled"
		DISABLE = NO
		FREE
		IRQ = 1
			SHARE = NO
			TRIGGER = EDGE
		PORT = 60h - 64h
			SHARE = "8042"
			SIZE = BYTE


FUNCTION = "Floppy Disk Controller"
  TYPE = "MSD,FPYCTL,FIFO"
  COMMENTS = "This controller is a superset of the typical ISA floppy disk
		controller.  It contains an internal FIFO and can support
		a maximum of two floppy drives.  Any combination of
		5 1/4 inch or 3 1/2 inch (non-PS/2) floppy drives may be used."
  HELP = "This section of the board can be disabled in order to
          allow the use of other cards that require this address range." 

  CHOICE = "Enabled as Primary Floppy Controller"
      FREE
        IRQ = 6
          SHARE = NO
          TRIGGER = EDGE
        PORT = 03f0h - 03f5h
          SIZE = BYTE
 	PORT = 03f6h - 03f7h
          SIZE = BYTE
	  SHARE = "ATtskfl"

	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000100	;c4h
	INIT = PORTADR(23h) 00000rr0	;Primary address
	INIT = PORTADR(22h) 11000000	;c0h
	INIT = PORTADR(23h) 00001rrr	;Enable Floppy Chip Select

	DMA = 2
          SIZE = BYTE
          TIMING = TYPEB

  CHOICE = "Enabled as Secondary Floppy Controller"
      FREE
        IRQ = 6
          SHARE = NO
          TRIGGER = EDGE
        PORT = 0370h - 0375h
          SIZE = BYTE
 	PORT = 0376h - 0377h
          SIZE = BYTE
	  SHARE = "ATtskfl"

	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000100	;c4h
	INIT = PORTADR(23h) 00000rr1	;Secondary address
	INIT = PORTADR(22h) 11000000	;c0h
	INIT = PORTADR(23h) 00001rrr	;Enable Floppy Chip Select

	DMA = 2
          SIZE = BYTE
          TIMING = TYPEB

  CHOICE = "Disabled"
    DISABLE = YES
    FREE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000000	;c0h
	INIT = PORTADR(23h) 00000rrr	;Disable Floppy Chip Select


FUNCTION = "Floppy Disk Controller Extended Registers"
  TYPE = "MSD,FPYCTL,EXT"
  COMMENTS = "This function is provided to allow the extended registers
  	of the embedded floppy controller to be made accessible to software."
  HELP = "Some software will malfunction if access to the extended registers
  	is allowed, other software will malfunction if the extended registers
	are not accessible.
	Therefore, the user must manually choose the option desired based upon
	empirical data."

  CHOICE = "Accessible"
	FREE

	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000100	;c4h
	INIT = PORTADR(23h) 00000r1r	;Enable access to 82077 Extended Reg.

  CHOICE = "Not accessible"
	FREE

	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000100	;c4h
	INIT = PORTADR(23h) 00000r0r	;Disable access to 82077 Extended Reg.


FUNCTION = "IDE Interface"
  TYPE = "MSD,IDE"
  COMMENTS = "The IDE interface is software compatible with a standard AT
              hard disk controller."
  HELP = "This section of the board can be disabled in order to
          allow the use of other cards that require this address range." 

  CHOICE = "Enabled at Primary Address"
      FREE
      IRQ = 14
        SHARE = NO 
        TRIGGER = EDGE
      PORT = 01f0h - 01f7h
        SIZE = BYTE
      PORT = 03f6h - 03f7h
	  SIZE = BYTE
	  SHARE = "ATtskfl"

	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11010000	;d0h
	INIT = PORTADR(23h) 00000111	;8 consecutive I/O addresses
	INIT = PORTADR(22h) 11010001	;d1h
	INIT = PORTADR(23h) 00000001	;2 consecutive I/O addresses
	INIT = PORTADR(22h) 11010100	;d4h
	INIT = PORTADR(23h) 11110000	;Low Order address - xxf0h
	INIT = PORTADR(22h) 11010101	;d5h
	INIT = PORTADR(23h) 11110110	;Low Order address - xxf6h
	INIT = PORTADR(22h) 11011000	;d8h
	INIT = PORTADR(23h) 00000001	;High Order address - 01xxh
	INIT = PORTADR(22h) 11011001	;d9h
	INIT = PORTADR(23h) 00000011	;High Order address - 03xxh

	INIT = PORTADR(22h) 11000100	;c4h
	INIT = PORTADR(23h) 000001rr	;Enable Buffer Control

	INIT = PORTADR(22h) 11000001	;c1h
	INIT = PORTADR(23h) rrrrrr11	;Enable Chip Selects

  CHOICE = "Enabled at Secondary Address"
     FREE
      IRQ = 14
        SHARE = NO 
        TRIGGER = EDGE
      PORT = 0170h - 0177h
        SIZE = BYTE
      PORT = 0376h - 0377h
        SIZE = BYTE
        SHARE = "ATtskfl"

	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11010000	;d0h
	INIT = PORTADR(23h) 00000111	;8 consecutive I/O addresses
	INIT = PORTADR(22h) 11010001	;d1h
	INIT = PORTADR(23h) 00000001	;2 consecutive I/O addresses
	INIT = PORTADR(22h) 11010100	;d4h
	INIT = PORTADR(23h) 01110000	;Low Order address - xx70h
	INIT = PORTADR(22h) 11010101	;d5h
	INIT = PORTADR(23h) 01110110	;Low Order address - xx76h
	INIT = PORTADR(22h) 11011000	;d8h
	INIT = PORTADR(23h) 00000001	;High Order address - 01xxh
	INIT = PORTADR(22h) 11011001	;d9h
	INIT = PORTADR(23h) 00000011	;High Order address - 03xxh

	INIT = PORTADR(22h) 11000100	;c4h
	INIT = PORTADR(23h) 000001rr	;Enable Buffer Control

	INIT = PORTADR(22h) 11000001	;c1h
	INIT = PORTADR(23h) rrrrrr11	;Enable Chip Selects

  CHOICE = "Disabled"
      DISABLE = YES
      FREE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000001	;c1h
	INIT = PORTADR(23h) rrrrrr00	;Disable Chip Selects

	INIT = PORTADR(22h) 11000100	;c4h
	INIT = PORTADR(23h) 000000rr	;Allow only D7 from Floppy


FUNCTION = "Parallel port"
  TYPE = "PAR"
  COMMENTS = "The parallel port has a standard 25 pin connector (AT style)
  	and is a superset of a typical ISA parallel port."
  HELP = "This section of the board can be disabled in order to
          allow the use of other cards that require this address range." 

  CHOICE = "Enabled as LPT1"
      SUBTYPE = "LPT1"
      FREE
        IRQ = 7
          SHARE = NO
          TRIGGER = EDGE
	INIT = PORTADR(22h) 00100001		;21h - ID register
	INIT = PORTADR(23h) 00000010		;Allow access to LIO.E
	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 00000rrr		;Edge Mode Interrupt

	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 0000r0rr		;PC/AT compatible mode

        PORT = 03bch - 03bfh
          SIZE = BYTE
	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 0000rr00		;LPT1 enable

  CHOICE = "Enabled as LPT2"
      SUBTYPE = "LPT2"
      FREE
        IRQ = 5
          SHARE = NO
          TRIGGER = EDGE
	INIT = PORTADR(22h) 00100001		;21h - ID register
	INIT = PORTADR(23h) 00000010		;Allow access to LIO.E
	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 00000rrr		;Edge Mode Interrupt

	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 0000r0rr		;PC/AT compatible mode

        PORT = 0378h - 037fh
          SIZE = BYTE
	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 0000rr01		;LPT2 enable

  CHOICE = "Enabled as LPT3"
      SUBTYPE = "LPT3"
      FREE
        IRQ = 5
          SHARE = NO
          TRIGGER = EDGE
	INIT = PORTADR(22h) 00100001		;21h - ID register
	INIT = PORTADR(23h) 00000010		;Allow access to LIO.E
	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 00000rrr		;Edge Mode Interrupt

	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 0000r0rr		;PC/AT compatible mode

        PORT = 0278h - 027fh
          SIZE = BYTE
	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 0000rr10		;LPT3 enable

  CHOICE = "Disabled"
    DISABLE = YES
    FREE
	INIT = PORTADR(22h) 00100001		;21h - ID register
	INIT = PORTADR(23h) 00000010		;Allow access to LIO.E

	INIT = PORTADR(22h) 11000010		;c2h
	INIT = PORTADR(23h) 0000rr11		;Disable LPT


FUNCTION = "Serial port A"
  TYPE = "COM,ASY"
  COMMENTS = "This serial port has a standard 9 pin connector (AT style)
  	and is a superset of a typical ISA serial port."
  HELP = "This section of the board can be disabled in order to 
          allow the use of other cards that require this address range."

  CHOICE = "Enabled as COM1"
	SUBTYPE = "COM1"
	FREE
        IRQ = 4
          SHARE = NO
          TRIGGER = EDGE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) rrrr0000	;Edge Mode Interrupt
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) rr00000r	;Serial Port A Interrupt = COM1IRQ

        PORT = 03F8h - 03FFh
          SIZE = BYTE
	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rr0000rr	;Serial Port A Addr = 3f8h (COM1)
	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rrrr00r0	;Enable Serial Port A Chip Select

  CHOICE = "Enabled as COM3"
	SUBTYPE = "COM3"
	FREE
        IRQ = 4
          SHARE = NO
          TRIGGER = EDGE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) rrrr0000	;Edge Mode Interrupt
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) rr10000r	;Serial Port A Interrupt = COM3IRQ

        PORT = 03e8h - 03efh
          SIZE = BYTE
	INIT = PORTADR(22h) 11000110	;c6h
	INIT = PORTADR(23h) 11101000	;Low Order Address - xxe8h
	INIT = PORTADR(22h) 11000111	;c7h
	INIT = PORTADR(23h) 00000011	;High Order Address - 03xxh

	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rr1000rr	;Serial Port A Addr = COM3
	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rrrr00r0	;Enable Serial Port A Chip Select

  CHOICE = "Disabled"
     DISABLE = YES
      FREE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rrrr00r1	;Disable Serial Port A Chip Select


FUNCTION = "Serial port B"
  TYPE = "COM,ASY"
  COMMENTS = "This serial port has a standard 25 pin connector (XT style)
	and is a superset of a typical ISA serial port."
  HELP = "This section of the board can be disabled in order to 
          allow the use of other cards that require this address range."

  CHOICE = "Enabled as COM2"
      SUBTYPE = "COM2"
      FREE
        IRQ = 3
          SHARE = NO
          TRIGGER = EDGE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) rrrr0000	;Edge Mode Interrupt
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) 01rr000r	;Serial Port B Interrupt = COM2IRQ

        PORT = 02F8h - 02FFh
          SIZE = BYTE
	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) 01rr00rr	;Serial Port B Addr = 2f8h (COM2)
	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rrrr000r	;Enable Serial Port B Chip Select

  CHOICE = "Enabled as COM4"
      SUBTYPE = "COM4"
      FREE
        IRQ = 3
          SHARE = NO
          TRIGGER = EDGE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) rrrr0000	;Edge Mode Interrupt
	INIT = PORTADR(22h) 11000101	;c5h
	INIT = PORTADR(23h) 11rr000r	;Serial Port B Interrupt = COM4IRQ

        PORT = 02e8h - 02efh
          SIZE = BYTE
	INIT = PORTADR(22h) 11001000	;c8h
	INIT = PORTADR(23h) 11101000	;Low Order Address - xxe8h
	INIT = PORTADR(22h) 11001001	;c9h
	INIT = PORTADR(23h) 00000010	;High Order Address - 02xxh

	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) 11rr00rr	;Serial Port B Addr = COM4
	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rrrr000r	;Enable Serial Port B Chip Select

  CHOICE = "Disabled"
     DISABLE = YES
	FREE
	INIT = PORTADR(22h) 00100001	;21h - ID register
	INIT = PORTADR(23h) 00000010	;Allow access to LIO.E

	INIT = PORTADR(22h) 11000011	;c3h
	INIT = PORTADR(23h) rrrr001r	;Disable Serial Port B Chip Select


FUNCTION = "Serial Port Enhanced Registers"
  TYPE = "COM,ASY,ENH"
  COMMENTS = "This function is provided to allow the enhanced registers
  	of the embedded serial ports to be made accessible to software."
  HELP = "Some software will malfunction if access to the enhanced registers
  	is allowed, other software will malfunction if the enhanced registers
	are not accessible.
	Therefore, the user must manually choose the option desired based upon
	empirical data."

  CHOICE = "Not accessible"
	FREE

	INIT = IOPORT(3) LOC(2) 0	;Don't enable access to extra registers

  CHOICE = "Accessible"
	FREE

	INIT = IOPORT(3) LOC(2) 1	;Enable access to extra registers


FUNCTION = "Short INTR to i486 errata"
  TYPE = "CPU,i486,INTR,errata"
  COMMENTS = "This function is provided to help overcome the following
  	INTEL problem with the i486.  The INTEL errata states - 
	If INTR is negated before the first INTA cycle occurs,
  	the i486 processor may malfunction.  Latching and/or Filtering
	INTR will correct this situation."
  HELP = "Some software will malfunction if Latching and Filtering is
  	employed, other software will malfunction if only Filtering is used.
	Therefore, the user must manually choose the method desired based upon
	empirical data."

  CHOICE = "Filter INTR to i486"
	FREE

	INIT = IOPORT(3) LOC(1 0) 10	;only Filter INTR to CPU

  CHOICE = "Latch INTR to i486"
	FREE

	INIT = IOPORT(3) LOC(1 0) 01	;only Latch INTR to CPU

  CHOICE = "Latch and Filter INTR to i486"
	FREE

	INIT = IOPORT(3) LOC(1 0) 11	;Both Latch & Filter INTR to CPU

  CHOICE = "Neither Latch nor Filter INTR to i486"
	FREE

	INIT = IOPORT(3) LOC(1 0) 00	;Neither